diff options
| author | azidar | 2016-02-08 14:36:08 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:07 -0800 |
| commit | 666a193706308a6fbd6c8b4bd06cbc69ae4200a6 (patch) | |
| tree | bc39995652b4860f4b992570f1004efffd969a0b | |
| parent | 69597a7d57236bc43c964f7714bfa8ed53bf3bee (diff) | |
Bug fixes, close to getting correct rocket-firrtl.fir through
| -rw-r--r-- | build.sbt | 2 | ||||
| -rw-r--r-- | test/parser/invalids.fir | 13 | ||||
| -rw-r--r-- | test/parser/node.fir | 16 |
3 files changed, 30 insertions, 1 deletions
@@ -6,7 +6,7 @@ name := "firrtl" version := "0.1-SNAPSHOT" -scalaVersion := "2.11.4" +scalaVersion := "2.11.7" libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value diff --git a/test/parser/invalids.fir b/test/parser/invalids.fir new file mode 100644 index 00000000..65051832 --- /dev/null +++ b/test/parser/invalids.fir @@ -0,0 +1,13 @@ +; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s +; CHECK: Done! +circuit GCD : + module GCD : + input x : UInt<128> + input p : UInt<1> + input q : UInt<1> + input clk : Clock + wire w : UInt[3] + w is invalid + w[0] <= UInt(0) + w[1] <= UInt(0) + w[2] <= UInt(0) diff --git a/test/parser/node.fir b/test/parser/node.fir new file mode 100644 index 00000000..193aed88 --- /dev/null +++ b/test/parser/node.fir @@ -0,0 +1,16 @@ +; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s +; CHECK: Done! +circuit GCD : + module GCD : + input x : UInt<128> + input p : UInt<1> + input q : UInt<1> + input clk : Clock + reg addr : UInt, clk with : + reset => (UInt<1>("h0"), addr) + when p : + node T_1234 = bits(x, 63, 24) + addr <= T_1234 + when q : + node T_1380 = tail(x, 1) + addr <= T_1380 |