Added new test that breaks current parser. updated todo

2 files changed, 36 insertions, 8 deletions

diff --git a/TODO b/TODO
index 1f95a8ad..bf847a6f 100644
--- a/TODO
+++ b/TODO
@@ -1,5 +1,5 @@
 ================================================
-========== ADAM's BIG ASS TODO LIST ============
+========== ADAM's BIG ARSE TODO LIST ============
 ================================================
 
 ======== Current Tasks ========
@@ -7,16 +7,15 @@ on-reset
 Parser
    Error if incorrectly assign stuff, like use = instead of :=
    Update parser and update tests
+Change all primops to be strict on data widths
+Make instances always male, flip the bundles on declaration
+dlsh,drsh
    
 ======== Update Core ==========
-on-reset
-Change all primops to be strict on data widths
 Add source locaters
 Add Unit Tests for each pass
 
 ======== Check Passes ==========
-Parser
-   Error if incorrectly assign stuff, like use = instead of :=
 Well-formed high firrtl 
    Unique names per module
    No name can be a prefix of any other name.
@@ -40,13 +39,12 @@ Stephen:
       pin stephen on an example
 
 ======== Think About ========
-dlsh,drsh
-naming for split nodes
 subword accesses
+verilog style guide
+naming for split nodes
 annotation system
 zero-width wires
 expanding mems (consider changing defmem to be size, and element type)
-Make instances always male, flip the bundles on declaration
 Multi-streams for print statements/asserts (Jack)
 Consider def female node. (Patrick) 
 Talk to palmer/patrick about how writing passes is going to be supported
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
new file mode 100644
index 00000000..7198667a
--- /dev/null
+++ b/test/chisel3/ModuleVec.fir
@@ -0,0 +1,30 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit ModuleVec : 
+  module PlusOne : 
+    input in : UInt(32)
+    output out : UInt(32)
+    
+    node T_33 = UInt(1, 1)
+    node T_34 = add(in, T_33)
+    out := T_34
+  module PlusOne_25 : 
+    input in : UInt(32)
+    output out : UInt(32)
+    
+    node T_35 = UInt(1, 1)
+    node T_36 = add(in, T_35)
+    out := T_36
+  module ModuleVec : 
+    output ins : UInt(32)[2]
+    output outs : UInt(32)[2]
+    
+    inst T_37 of PlusOne
+    inst T_38 of PlusOne_25
+    wire pluses : {flip in : UInt(32), out : UInt(32)}[2]
+    pluses.0 := T_37
+    pluses.1 := T_38
+    pluses.s.in := ins.s
+    outs.0 := pluses.s.out
+    pluses.s.in := ins.1
+    outs.1 := pluses.1.out