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| author | Schuyler Eldridge | 2020-05-06 12:35:48 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-05-06 16:32:32 -0400 |
| commit | 21cf4cfa4bcf1d5febe5efd791633c8ea0185c6a (patch) | |
| tree | d1aa61893a910c1896d376f7f3e698d5425b081c | |
| parent | 6e5721442c067829ad1e5d0c2c5c52f4056c83b7 (diff) | |
Clarify spec indentation of when/else
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
| -rw-r--r-- | spec/spec.tex | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/spec/spec.tex b/spec/spec.tex index 9645e137..682c76a0 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -712,6 +712,30 @@ module MyModule : x <= d \end{lstlisting} +To additionally aid readability, a conditional statement where the contents of the \verb|when| branch consist of a single line may be combined into a single line. +If an \verb|else| branch exists, then the \verb|else| keyword must be included on the same line. + +The following statement: +\begin{lstlisting} +when c : + a <= b +else : + e <= f +\end{lstlisting} + +can have the \verb|when| keyword, the \verb|when| branch, and the \verb|else| keyword expressed as a single line: + +\begin{lstlisting} +when c : a <= b else : + e <= f +\end{lstlisting} + +The \verb|else| branch may also be added to the single line: + +\begin{lstlisting} +when c : a <= b else : e <= f +\end{lstlisting} + \subsubsection{Nested Declarations} If a component is declared within a conditional statement, connections to the component are unaffected by the condition. In the following example, register \verb|myreg1| is always connected to \verb|a|, and register \verb|myreg2| is always connected to \verb|b|. |