From 21cf4cfa4bcf1d5febe5efd791633c8ea0185c6a Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Wed, 6 May 2020 12:35:48 -0400
Subject: Clarify spec indentation of when/else

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 spec/spec.tex | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/spec/spec.tex b/spec/spec.tex
index 9645e137..682c76a0 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -712,6 +712,30 @@ module MyModule :
       x <= d
 \end{lstlisting}
 
+To additionally aid readability, a conditional statement where the contents of the \verb|when| branch consist of a single line may be combined into a single line.
+If an \verb|else| branch exists, then the \verb|else| keyword must be included on the same line.
+
+The following statement:
+\begin{lstlisting}
+when c :
+   a <= b
+else :
+   e <= f
+\end{lstlisting}
+
+can have the \verb|when| keyword, the \verb|when| branch, and the \verb|else| keyword expressed as a single line:
+
+\begin{lstlisting}
+when c : a <= b else :
+  e <= f
+\end{lstlisting}
+
+The \verb|else| branch may also be added to the single line:
+
+\begin{lstlisting}
+when c : a <= b else : e <= f
+\end{lstlisting}
+
 \subsubsection{Nested Declarations}
 If a component is declared within a conditional statement, connections to the component are unaffected by the condition. In the following example, register \verb|myreg1| is always connected to \verb|a|, and register \verb|myreg2| is always connected to \verb|b|.
 
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