Added test to show correctness of gender inference and lowering

3 files changed, 21 insertions, 10 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 964ede74..482765c3 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1037,7 +1037,7 @@ defn initialize-registers (c:Circuit) :
    defn explicit-init-scope (s:Stmt) -> Stmt :
       val h = HashTable<Symbol,True|False>(symbol-hash)
       using-init(s,h)
-      println(h)
+      ;println(h)
       val [s* t] = rename(s,h)
       add-when(s*,t)
      
@@ -1395,14 +1395,14 @@ defn expand-whens (m:Module) -> Module :
    val enables = get-enables(assign,kinds)
    for x in enables do : enables[key(x)] = optimize(value(x))
          
-   println("Assigns")
-   for x in assign do : println(x)
-   println("Kinds")
-   for x in kinds do : println(x)
-   println("Decs")
-   for x in decs do : println(x)
-   println("Enables")
-   for x in enables do : println(x)
+   ;println("Assigns")
+   ;for x in assign do : println(x)
+   ;println("Kinds")
+   ;for x in kinds do : println(x)
+   ;println("Decs")
+   ;for x in decs do : println(x)
+   ;println("Enables")
+   ;for x in enables do : println(x)
 
    Module(name(m),ports(m),expand-whens(assign,kinds,stmts,decs,enables))
 
diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir
index 4a516924..2a66062f 100644
--- a/test/passes/resolve-genders/bigenders.fir
+++ b/test/passes/resolve-genders/bigenders.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcdefghipj cg | tee %s.out | FileCheck %s
+; RUN: firrtl %s abcdefghipj c | tee %s.out | FileCheck %s
 
 ;CHECK: Resolve Genders
 circuit top :
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
new file mode 100644
index 00000000..247251ae
--- /dev/null
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -0,0 +1,11 @@
+; RUN: firrtl %s abcdefghipj c | tee %s.out | FileCheck %s
+
+;CHECK: Lower To Ground
+circuit top :
+   module M :
+      wire w : { flip x : UInt(10)}
+      reg r : { flip x : UInt(10)}
+      w := r     ; CHECK r$x := w$x
+      w.x := r.x ; CHECK w$x := r$x
+; CHECK: Finished Lower To Ground
+