blob: 4a516924d539ecbb594d09713ed4ce59d9a1d701 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
|
; RUN: firrtl %s abcdefghipj cg | tee %s.out | FileCheck %s
;CHECK: Resolve Genders
circuit top :
module M :
input i : UInt(10)
output o : UInt(10)
wire w : {x : UInt(10), flip y : UInt(10)}
w.x := i
w.y := i
o := w.x
o := w.y
; CHECK: Finished Resolve Genders
|
