blob: f84c787911f36ab6543f5cd9c3037d71eac0c9d8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
|
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header
#include "Vtb.h"
#include "Vtb__Syms.h"
//==========
void Vtb::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vtb::eval\n"); );
Vtb__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT("tb.v", 6, "",
"Verilated model didn't converge\n"
"- See DIDNOTCONVERGE in the Verilator manual");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void Vtb::_eval_initial_loop(Vtb__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT("tb.v", 6, "",
"Verilated model didn't DC converge\n"
"- See DIDNOTCONVERGE in the Verilator manual");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void Vtb::_eval(Vtb__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_eval\n"); );
Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
VL_INLINE_OPT QData Vtb::_change_request(Vtb__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_change_request\n"); );
Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
return (vlTOPp->_change_request_1(vlSymsp));
}
VL_INLINE_OPT QData Vtb::_change_request_1(Vtb__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_change_request_1\n"); );
Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
__req |= ((vlTOPp->tb__DOT__val1 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val1)
| (vlTOPp->tb__DOT__val2 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val2));
VL_DEBUG_IF( if(__req && ((vlTOPp->tb__DOT__val1 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val1))) VL_DBG_MSGF(" CHANGE: tb.v:10: tb.val1\n"); );
VL_DEBUG_IF( if(__req && ((vlTOPp->tb__DOT__val2 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val2))) VL_DBG_MSGF(" CHANGE: tb.v:11: tb.val2\n"); );
// Final
vlTOPp->__Vchglast__TOP__tb__DOT__val1 = vlTOPp->tb__DOT__val1;
vlTOPp->__Vchglast__TOP__tb__DOT__val2 = vlTOPp->tb__DOT__val2;
return __req;
}
#ifdef VL_DEBUG
void Vtb::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_eval_debug_assertions\n"); );
}
#endif // VL_DEBUG
|
