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authorAditya Naik2021-05-08 12:51:18 -0400
committerAditya Naik2021-05-08 12:51:18 -0400
commit1acccc74b1036d9d3847fdcc60c392125a03be85 (patch)
tree609c192f1b3e1b4ab89e1992741d988f4120138c /core/obj_dir/Vtb.cpp
Initial
Added work on RV64 I core to date, including tb
Diffstat (limited to 'core/obj_dir/Vtb.cpp')
-rw-r--r--core/obj_dir/Vtb.cpp99
1 files changed, 99 insertions, 0 deletions
diff --git a/core/obj_dir/Vtb.cpp b/core/obj_dir/Vtb.cpp
new file mode 100644
index 0000000..f84c787
--- /dev/null
+++ b/core/obj_dir/Vtb.cpp
@@ -0,0 +1,99 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vtb.h for the primary calling header
+
+#include "Vtb.h"
+#include "Vtb__Syms.h"
+
+//==========
+
+void Vtb::eval_step() {
+ VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vtb::eval\n"); );
+ Vtb__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
+ Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+#ifdef VL_DEBUG
+ // Debug assertions
+ _eval_debug_assertions();
+#endif // VL_DEBUG
+ // Initialize
+ if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
+ // Evaluate till stable
+ int __VclockLoop = 0;
+ QData __Vchange = 1;
+ do {
+ VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
+ _eval(vlSymsp);
+ if (VL_UNLIKELY(++__VclockLoop > 100)) {
+ // About to fail, so enable debug to see what's not settling.
+ // Note you must run make with OPT=-DVL_DEBUG for debug prints.
+ int __Vsaved_debug = Verilated::debug();
+ Verilated::debug(1);
+ __Vchange = _change_request(vlSymsp);
+ Verilated::debug(__Vsaved_debug);
+ VL_FATAL_MT("tb.v", 6, "",
+ "Verilated model didn't converge\n"
+ "- See DIDNOTCONVERGE in the Verilator manual");
+ } else {
+ __Vchange = _change_request(vlSymsp);
+ }
+ } while (VL_UNLIKELY(__Vchange));
+}
+
+void Vtb::_eval_initial_loop(Vtb__Syms* __restrict vlSymsp) {
+ vlSymsp->__Vm_didInit = true;
+ _eval_initial(vlSymsp);
+ // Evaluate till stable
+ int __VclockLoop = 0;
+ QData __Vchange = 1;
+ do {
+ _eval_settle(vlSymsp);
+ _eval(vlSymsp);
+ if (VL_UNLIKELY(++__VclockLoop > 100)) {
+ // About to fail, so enable debug to see what's not settling.
+ // Note you must run make with OPT=-DVL_DEBUG for debug prints.
+ int __Vsaved_debug = Verilated::debug();
+ Verilated::debug(1);
+ __Vchange = _change_request(vlSymsp);
+ Verilated::debug(__Vsaved_debug);
+ VL_FATAL_MT("tb.v", 6, "",
+ "Verilated model didn't DC converge\n"
+ "- See DIDNOTCONVERGE in the Verilator manual");
+ } else {
+ __Vchange = _change_request(vlSymsp);
+ }
+ } while (VL_UNLIKELY(__Vchange));
+}
+
+void Vtb::_eval(Vtb__Syms* __restrict vlSymsp) {
+ VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_eval\n"); );
+ Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+}
+
+VL_INLINE_OPT QData Vtb::_change_request(Vtb__Syms* __restrict vlSymsp) {
+ VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_change_request\n"); );
+ Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+ // Body
+ return (vlTOPp->_change_request_1(vlSymsp));
+}
+
+VL_INLINE_OPT QData Vtb::_change_request_1(Vtb__Syms* __restrict vlSymsp) {
+ VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_change_request_1\n"); );
+ Vtb* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+ // Body
+ // Change detection
+ QData __req = false; // Logically a bool
+ __req |= ((vlTOPp->tb__DOT__val1 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val1)
+ | (vlTOPp->tb__DOT__val2 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val2));
+ VL_DEBUG_IF( if(__req && ((vlTOPp->tb__DOT__val1 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val1))) VL_DBG_MSGF(" CHANGE: tb.v:10: tb.val1\n"); );
+ VL_DEBUG_IF( if(__req && ((vlTOPp->tb__DOT__val2 ^ vlTOPp->__Vchglast__TOP__tb__DOT__val2))) VL_DBG_MSGF(" CHANGE: tb.v:11: tb.val2\n"); );
+ // Final
+ vlTOPp->__Vchglast__TOP__tb__DOT__val1 = vlTOPp->tb__DOT__val1;
+ vlTOPp->__Vchglast__TOP__tb__DOT__val2 = vlTOPp->tb__DOT__val2;
+ return __req;
+}
+
+#ifdef VL_DEBUG
+void Vtb::_eval_debug_assertions() {
+ VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb::_eval_debug_assertions\n"); );
+}
+#endif // VL_DEBUG