aboutsummaryrefslogtreecommitdiff
path: root/pcb/base/openmano-hw.sch
blob: a075b41e6b93c521a85a58e39f11c4d3d2326f12 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 4
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 5630 1390 1440 1510
U 608364CF
F0 "mcu" 50
F1 "mcu.sch" 50
F2 "BAT_SENSE" I L 5630 1550 50 
F3 "VBAT_CC" I L 5630 1660 50 
F4 "MPY_UART1_TX" I L 5630 2300 50 
F5 "MPY_UART1_RX" I L 5630 2400 50 
F6 "MPY_SPI1_CS" I L 5630 2200 50 
F7 "MPY_SPI1_MISO" I L 5630 2000 50 
F8 "MPY_SPI1_MOSI" I L 5630 2100 50 
F9 "GPIO0" I R 7070 1970 50 
F10 "GPIO1" I R 7070 2070 50 
F11 "GPIO2" I R 7070 2170 50 
F12 "GPIO3" I R 7070 2270 50 
F13 "GPIO4" I R 7070 2370 50 
F14 "GPIO5" I R 7070 2470 50 
F15 "GPIO6" I R 7070 2570 50 
F16 "GPIO7" I R 7070 2670 50 
F17 "MPY_SPI1_SCLK" I L 5630 1900 50 
$EndSheet
$Sheet
S 3820 1430 970  360 
U 608AF7DB
F0 "power" 50
F1 "power.sch" 50
F2 "VBAT_CC" I R 4790 1660 50 
F3 "BAT_SENSE" O R 4790 1550 50 
$EndSheet
Entry Wire Line
	7420 1970 7520 2070
Entry Wire Line
	7420 2070 7520 2170
Entry Wire Line
	7420 2170 7520 2270
Entry Wire Line
	7420 2270 7520 2370
Entry Wire Line
	7420 2370 7520 2470
Entry Wire Line
	7420 2470 7520 2570
Entry Wire Line
	7420 2570 7520 2670
Entry Wire Line
	7420 2670 7520 2770
Text Label 7180 1970 0    50   ~ 0
GPIO0
Text Label 7180 2070 0    50   ~ 0
GPIO1
Text Label 7180 2170 0    50   ~ 0
GPIO2
Text Label 7180 2270 0    50   ~ 0
GPIO3
Text Label 7180 2370 0    50   ~ 0
GPIO4
Text Label 7180 2470 0    50   ~ 0
GPIO5
Text Label 7180 2570 0    50   ~ 0
GPIO6
Text Label 7180 2670 0    50   ~ 0
GPIO7
Wire Wire Line
	7070 1970 7420 1970
Wire Wire Line
	7070 2070 7420 2070
Wire Wire Line
	7070 2170 7420 2170
Wire Wire Line
	7070 2270 7420 2270
Wire Wire Line
	7070 2370 7420 2370
Wire Wire Line
	7070 2470 7420 2470
Wire Wire Line
	7070 2570 7420 2570
Wire Wire Line
	7070 2670 7420 2670
Entry Wire Line
	7420 3830 7520 3930
Entry Wire Line
	7420 3930 7520 4030
Entry Wire Line
	7420 4030 7520 4130
Entry Wire Line
	7420 4130 7520 4230
Entry Wire Line
	7420 4230 7520 4330
Entry Wire Line
	7420 4330 7520 4430
Entry Wire Line
	7420 4430 7520 4530
Text Label 7120 3830 0    50   ~ 0
GPIO1
Text Label 7120 3930 0    50   ~ 0
GPIO2
Text Label 7120 4030 0    50   ~ 0
GPIO3
Text Label 7120 4130 0    50   ~ 0
GPIO4
Text Label 7120 4230 0    50   ~ 0
GPIO5
Text Label 7120 4330 0    50   ~ 0
GPIO6
Text Label 7120 4430 0    50   ~ 0
GPIO7
$Sheet
S 5630 3630 1440 970 
U 608893F4
F0 "peripherals" 50
F1 "peripherals.sch" 50
F2 "SPI1_SCLK" I L 5630 3730 50 
F3 "SPI1_MISO" I L 5630 3830 50 
F4 "SPI1_MOSI" I L 5630 3930 50 
F5 "SPI1_CS" I L 5630 4030 50 
F6 "UART1_TX" I L 5630 4130 50 
F7 "UART1_RX" I L 5630 4230 50 
F8 "GPIO0" I R 7070 3720 50 
F9 "GPIO1" I R 7070 3830 50 
F10 "GPIO2" I R 7070 3930 50 
F11 "GPIO3" I R 7070 4030 50 
F12 "GPIO4" I R 7070 4130 50 
F13 "GPIO5" I R 7070 4230 50 
F14 "GPIO6" I R 7070 4330 50 
F15 "GPIO7" I R 7070 4430 50 
$EndSheet
Entry Wire Line
	5190 1800 5290 1900
Entry Wire Line
	5190 1900 5290 2000
Entry Wire Line
	5190 2000 5290 2100
Entry Wire Line
	5190 2100 5290 2200
Entry Wire Line
	5190 2200 5290 2300
Entry Wire Line
	5190 2300 5290 2400
Wire Wire Line
	5290 1900 5630 1900
Wire Wire Line
	5290 2000 5630 2000
Wire Wire Line
	5290 2100 5630 2100
Wire Wire Line
	5290 2200 5630 2200
Wire Wire Line
	5290 2300 5630 2300
Wire Wire Line
	5290 2400 5630 2400
Entry Wire Line
	5190 3630 5290 3730
Entry Wire Line
	5190 3730 5290 3830
Entry Wire Line
	5190 3830 5290 3930
Entry Wire Line
	5190 3930 5290 4030
Entry Wire Line
	5190 4030 5290 4130
Entry Wire Line
	5190 4130 5290 4230
Wire Wire Line
	5290 3730 5630 3730
Wire Wire Line
	5290 3830 5630 3830
Wire Wire Line
	5290 3930 5630 3930
Wire Wire Line
	5290 4030 5630 4030
Wire Wire Line
	5290 4130 5630 4130
Wire Wire Line
	5290 4230 5630 4230
Text Label 5590 3730 2    50   ~ 0
SPI_SCLK
Text Label 5580 3830 2    50   ~ 0
SPI_MISO
Text Label 5570 3930 2    50   ~ 0
SPI_MOSI
Text Label 5580 4030 2    50   ~ 0
SPI_CS
Text Label 5580 4130 2    50   ~ 0
UART_TX
Text Label 5580 4230 2    50   ~ 0
UART_RX
Text Label 5580 1900 2    50   ~ 0
SPI_SCLK
Text Label 5580 2000 2    50   ~ 0
SPI_MISO
Text Label 5590 2100 2    50   ~ 0
SPI_MOSI
Text Label 5580 2200 2    50   ~ 0
SPI_CS
Text Label 5580 2300 2    50   ~ 0
UART_TX
Text Label 5580 2400 2    50   ~ 0
UART_RX
Wire Wire Line
	4790 1550 5630 1550
Wire Wire Line
	4790 1660 5630 1660
Entry Wire Line
	7420 3720 7520 3820
Wire Wire Line
	7420 3720 7070 3720
Text Label 7130 3720 0    50   ~ 0
GPIO0
Wire Wire Line
	7420 3830 7070 3830
Wire Wire Line
	7420 3930 7070 3930
Wire Wire Line
	7420 4030 7070 4030
Wire Wire Line
	7420 4130 7070 4130
Wire Wire Line
	7420 4230 7070 4230
Wire Wire Line
	7420 4330 7070 4330
Wire Wire Line
	7420 4430 7070 4430
Wire Bus Line
	5190 1760 5190 4640
Wire Bus Line
	7520 1920 7520 4620
$EndSCHEMATC