diff options
Diffstat (limited to 'pcb/base/openmano-hw.sch')
| -rw-r--r-- | pcb/base/openmano-hw.sch | 242 |
1 files changed, 242 insertions, 0 deletions
diff --git a/pcb/base/openmano-hw.sch b/pcb/base/openmano-hw.sch new file mode 100644 index 0000000..a075b41 --- /dev/null +++ b/pcb/base/openmano-hw.sch @@ -0,0 +1,242 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 4 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Sheet +S 5630 1390 1440 1510 +U 608364CF +F0 "mcu" 50 +F1 "mcu.sch" 50 +F2 "BAT_SENSE" I L 5630 1550 50 +F3 "VBAT_CC" I L 5630 1660 50 +F4 "MPY_UART1_TX" I L 5630 2300 50 +F5 "MPY_UART1_RX" I L 5630 2400 50 +F6 "MPY_SPI1_CS" I L 5630 2200 50 +F7 "MPY_SPI1_MISO" I L 5630 2000 50 +F8 "MPY_SPI1_MOSI" I L 5630 2100 50 +F9 "GPIO0" I R 7070 1970 50 +F10 "GPIO1" I R 7070 2070 50 +F11 "GPIO2" I R 7070 2170 50 +F12 "GPIO3" I R 7070 2270 50 +F13 "GPIO4" I R 7070 2370 50 +F14 "GPIO5" I R 7070 2470 50 +F15 "GPIO6" I R 7070 2570 50 +F16 "GPIO7" I R 7070 2670 50 +F17 "MPY_SPI1_SCLK" I L 5630 1900 50 +$EndSheet +$Sheet +S 3820 1430 970 360 +U 608AF7DB +F0 "power" 50 +F1 "power.sch" 50 +F2 "VBAT_CC" I R 4790 1660 50 +F3 "BAT_SENSE" O R 4790 1550 50 +$EndSheet +Entry Wire Line + 7420 1970 7520 2070 +Entry Wire Line + 7420 2070 7520 2170 +Entry Wire Line + 7420 2170 7520 2270 +Entry Wire Line + 7420 2270 7520 2370 +Entry Wire Line + 7420 2370 7520 2470 +Entry Wire Line + 7420 2470 7520 2570 +Entry Wire Line + 7420 2570 7520 2670 +Entry Wire Line + 7420 2670 7520 2770 +Text Label 7180 1970 0 50 ~ 0 +GPIO0 +Text Label 7180 2070 0 50 ~ 0 +GPIO1 +Text Label 7180 2170 0 50 ~ 0 +GPIO2 +Text Label 7180 2270 0 50 ~ 0 +GPIO3 +Text Label 7180 2370 0 50 ~ 0 +GPIO4 +Text Label 7180 2470 0 50 ~ 0 +GPIO5 +Text Label 7180 2570 0 50 ~ 0 +GPIO6 +Text Label 7180 2670 0 50 ~ 0 +GPIO7 +Wire Wire Line + 7070 1970 7420 1970 +Wire Wire Line + 7070 2070 7420 2070 +Wire Wire Line + 7070 2170 7420 2170 +Wire Wire Line + 7070 2270 7420 2270 +Wire Wire Line + 7070 2370 7420 2370 +Wire Wire Line + 7070 2470 7420 2470 +Wire Wire Line + 7070 2570 7420 2570 +Wire Wire Line + 7070 2670 7420 2670 +Entry Wire Line + 7420 3830 7520 3930 +Entry Wire Line + 7420 3930 7520 4030 +Entry Wire Line + 7420 4030 7520 4130 +Entry Wire Line + 7420 4130 7520 4230 +Entry Wire Line + 7420 4230 7520 4330 +Entry Wire Line + 7420 4330 7520 4430 +Entry Wire Line + 7420 4430 7520 4530 +Text Label 7120 3830 0 50 ~ 0 +GPIO1 +Text Label 7120 3930 0 50 ~ 0 +GPIO2 +Text Label 7120 4030 0 50 ~ 0 +GPIO3 +Text Label 7120 4130 0 50 ~ 0 +GPIO4 +Text Label 7120 4230 0 50 ~ 0 +GPIO5 +Text Label 7120 4330 0 50 ~ 0 +GPIO6 +Text Label 7120 4430 0 50 ~ 0 +GPIO7 +$Sheet +S 5630 3630 1440 970 +U 608893F4 +F0 "peripherals" 50 +F1 "peripherals.sch" 50 +F2 "SPI1_SCLK" I L 5630 3730 50 +F3 "SPI1_MISO" I L 5630 3830 50 +F4 "SPI1_MOSI" I L 5630 3930 50 +F5 "SPI1_CS" I L 5630 4030 50 +F6 "UART1_TX" I L 5630 4130 50 +F7 "UART1_RX" I L 5630 4230 50 +F8 "GPIO0" I R 7070 3720 50 +F9 "GPIO1" I R 7070 3830 50 +F10 "GPIO2" I R 7070 3930 50 +F11 "GPIO3" I R 7070 4030 50 +F12 "GPIO4" I R 7070 4130 50 +F13 "GPIO5" I R 7070 4230 50 +F14 "GPIO6" I R 7070 4330 50 +F15 "GPIO7" I R 7070 4430 50 +$EndSheet +Entry Wire Line + 5190 1800 5290 1900 +Entry Wire Line + 5190 1900 5290 2000 +Entry Wire Line + 5190 2000 5290 2100 +Entry Wire Line + 5190 2100 5290 2200 +Entry Wire Line + 5190 2200 5290 2300 +Entry Wire Line + 5190 2300 5290 2400 +Wire Wire Line + 5290 1900 5630 1900 +Wire Wire Line + 5290 2000 5630 2000 +Wire Wire Line + 5290 2100 5630 2100 +Wire Wire Line + 5290 2200 5630 2200 +Wire Wire Line + 5290 2300 5630 2300 +Wire Wire Line + 5290 2400 5630 2400 +Entry Wire Line + 5190 3630 5290 3730 +Entry Wire Line + 5190 3730 5290 3830 +Entry Wire Line + 5190 3830 5290 3930 +Entry Wire Line + 5190 3930 5290 4030 +Entry Wire Line + 5190 4030 5290 4130 +Entry Wire Line + 5190 4130 5290 4230 +Wire Wire Line + 5290 3730 5630 3730 +Wire Wire Line + 5290 3830 5630 3830 +Wire Wire Line + 5290 3930 5630 3930 +Wire Wire Line + 5290 4030 5630 4030 +Wire Wire Line + 5290 4130 5630 4130 +Wire Wire Line + 5290 4230 5630 4230 +Text Label 5590 3730 2 50 ~ 0 +SPI_SCLK +Text Label 5580 3830 2 50 ~ 0 +SPI_MISO +Text Label 5570 3930 2 50 ~ 0 +SPI_MOSI +Text Label 5580 4030 2 50 ~ 0 +SPI_CS +Text Label 5580 4130 2 50 ~ 0 +UART_TX +Text Label 5580 4230 2 50 ~ 0 +UART_RX +Text Label 5580 1900 2 50 ~ 0 +SPI_SCLK +Text Label 5580 2000 2 50 ~ 0 +SPI_MISO +Text Label 5590 2100 2 50 ~ 0 +SPI_MOSI +Text Label 5580 2200 2 50 ~ 0 +SPI_CS +Text Label 5580 2300 2 50 ~ 0 +UART_TX +Text Label 5580 2400 2 50 ~ 0 +UART_RX +Wire Wire Line + 4790 1550 5630 1550 +Wire Wire Line + 4790 1660 5630 1660 +Entry Wire Line + 7420 3720 7520 3820 +Wire Wire Line + 7420 3720 7070 3720 +Text Label 7130 3720 0 50 ~ 0 +GPIO0 +Wire Wire Line + 7420 3830 7070 3830 +Wire Wire Line + 7420 3930 7070 3930 +Wire Wire Line + 7420 4030 7070 4030 +Wire Wire Line + 7420 4130 7070 4130 +Wire Wire Line + 7420 4230 7070 4230 +Wire Wire Line + 7420 4330 7070 4330 +Wire Wire Line + 7420 4430 7070 4430 +Wire Bus Line + 5190 1760 5190 4640 +Wire Bus Line + 7520 1920 7520 4620 +$EndSCHEMATC |