diff options
| author | Aditya Naik | 2021-08-27 13:07:37 -0400 |
|---|---|---|
| committer | Aditya Naik | 2021-08-27 13:07:37 -0400 |
| commit | 663e24a3d8f45b4b184b3a4bc3a57bc0f3d6cd78 (patch) | |
| tree | 62a699a6065bea9f4bcefda93d227209fec4a154 /handwritten_support/hgen/lexer.hgen | |
Initial; working SAIL RISC-V regs
The register definition along with read/write functions for registers
are lowered to Coq. The FIRRTL annotation does not work as expected.
Diffstat (limited to 'handwritten_support/hgen/lexer.hgen')
| -rw-r--r-- | handwritten_support/hgen/lexer.hgen | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/handwritten_support/hgen/lexer.hgen b/handwritten_support/hgen/lexer.hgen new file mode 100644 index 0000000..9009f33 --- /dev/null +++ b/handwritten_support/hgen/lexer.hgen @@ -0,0 +1,63 @@ +(** RV32I (and RV64I) ***********************************************) +"lui" , UTYPE { op=RISCVLUI }; +"auipc" , UTYPE { op=RISCVAUIPC }; + +"jal", JAL (); +"jalr", JALR (); + +"beq", BTYPE {op=RISCVBEQ}; +"bne", BTYPE {op=RISCVBNE}; +"blt", BTYPE {op=RISCVBLT}; +"bge", BTYPE {op=RISCVBGE}; +"bltu", BTYPE {op=RISCVBLTU}; +"bgeu", BTYPE {op=RISCVBGEU}; + +"addi", ITYPE {op=RISCVADDI}; +"stli", ITYPE {op=RISCVSLTI}; +"sltiu", ITYPE {op=RISCVSLTIU}; +"xori", ITYPE {op=RISCVXORI}; +"ori", ITYPE {op=RISCVORI}; +"andi", ITYPE {op=RISCVANDI}; + +"add", RTYPE {op=RISCVADD}; +"sub", RTYPE {op=RISCVSUB}; +"sll", RTYPE {op=RISCVSLL}; +"slt", RTYPE {op=RISCVSLT}; +"sltu", RTYPE {op=RISCVSLT}; +"xor", RTYPE {op=RISCVXOR}; +"srl", RTYPE {op=RISCVSRL}; +"sra", RTYPE {op=RISCVSRA}; +"or", RTYPE {op=RISCVOR}; +"and", RTYPE {op=RISCVAND}; + +"fence", FENCE (); +"fence.tso", FENCETSO (); +"fence.i", FENCEI (); + +(** RV64I (in addition to RV32I) ************************************) + +"addiw", ADDIW (); + +"addw", RTYPEW {op=RISCVADDW}; +"subw", RTYPEW {op=RISCVSUBW}; +"sllw", RTYPEW {op=RISCVSLLW}; +"srlw", RTYPEW {op=RISCVSRLW}; +"sraw", RTYPEW {op=RISCVSRAW}; + +"slli", SHIFTIOP {op=RISCVSLLI}; +"srli", SHIFTIOP {op=RISCVSRLI}; +"srai", SHIFTIOP {op=RISCVSRAI}; + +"slliw", SHIFTW {op=RISCVSLLI}; +"srliw", SHIFTW {op=RISCVSRLI}; +"sraiw", SHIFTW {op=RISCVSRAI}; + +(** RV32A (and RV64A) ***********************************************) + +"r", FENCEOPTION Fence_R; +"w", FENCEOPTION Fence_W; +"rw", FENCEOPTION Fence_RW; + +(** pseudo instructions *********************************************) + +"li", LI () |