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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Change top.cpp to deassert reset one time unit before the clock asserts.
This avoids a Verilator simultation issue in top.cpp where the eval()
function is only called once per simultation loop. If the clock and
reset are both changed and eval() is only called once, then any
combinational update due to a change in reset is not visible to the
sequential logic. This avoids issues where the downstream compilation
utilities move synchronous reset logic outside of an always block that
describes a synchronous reset flip flop.
Reset now deasserts on time unit 10 and the clock ticks on time unit
11.
h/t @albert-magyar
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Change a test to use emitChirrtl instead of emitFirrtl. This test
isn't supposed to be running the Scala FIRRTL Compiler, but the latter
method causes this to happen.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This annotation adds memory import with inline generation for the
emmiter.
Supports both readmemh and readmemb statements based on argument.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Handle MemTypeBinding in Analog
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Fix stack trace trimming across ChiselStage
Fix bug in stack trace trimming behavior. Now, the following is what
happens:
1. The Builder, if catching accumulated errors, will now throw a
ChiselException with a Scala-trimmed Stack trace. Previously, this
would throw the full excpetion.
2. The Elaborate phase handles stack trace trimming. By default, any
Throwable thrown during elaboration will have its stack
trace *mutably* trimmed and is rethrown. A logger.error is printed
stating that there was an error during elaboration and how the user
can turn on the full stack trace. If the --full-stacktrace option
is on, then the Throwable is not caught and only the first
logger.error (saying that elaboration failed) will be printed.
3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain
all inherit the behavior of (2).
Mutable stack trace trimming behavior is moved into an implicit
class (previously this was defined on ChiselException only) so this
can be applied to any Throwable.
No StageErrors are now thrown anymore. However, StageErrors may still
be caught by ChiselMain (since it is a StageMain).
Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test
all this behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.
* Add MemTypeBinding for port types of Mems
This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.
* Call _onModuleClose on unbound Records
This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
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This is a new SBT build unit that symlinks in some files from the normal
chisel project tests, but builds them without the compiler plugin.
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* Added SyncReadMem-based implementation of the Queue class
* Rework of the parametrized Queue class SyncReadMem-based implementation
* Modification of the parametrized Queue class SyncReadMem-based implementation
* Limiting the visibility of the read address for SyncReadMem-based Queue
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Update reported width from div/rem to match FIRRTL results
* Add tests for width of % and / on UInt and SInt
* Add loop-based test for known UInt/SInt op result widths
Co-authored-by: Jack Koenig <koenig@sifive.com>
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If a method passed to higher function does not return any value,
it is prefer to use `foreach` instead of `map`.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.
Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.
Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
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This is useful for libraries to guard operations implemented via
annotations or BlackBoxes by the current when predicate
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serialize properly) (#1714)
* Add (failing) Test for Data toTarget calls
Add scaladoc and clean up test
* Builder: don't let .toTarget pass if it won't be able to deserialize properly later
* Update src/test/scala/chiselTests/ReferenceTargetSpec.scala
* Rename and simplify tests for literal toTarget
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(#1670)
* Builder: use LazyLogging.logger.warn to print elaboration message
* add deprecation for chisel3.internal.ErrorLog.info.
* add test to check elaboration message still exist.
Co-authored-by: Kevin Laeufer <kevin.laeufer@sifive.com>
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Implemented by folding Element.ref into Data.ref. Element.ref had
special handling for literals, but because Bundles can also be literals,
there were code paths that tried to get the ref of a Bundle literal
which was non-existent. Now, all literals are handled together.
Because FIRRTL does not have support for Bundle literals, Bundle literal
refs are implemented by materializing a Wire.
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* Improve source locators for switch statements.
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The SecurityManager is global so is not thread-safe. This is the source
of flaky tests in FIRRTL CI.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Refine autonaming to have more intuitive behavior
Last name in an Expression wins, while the first Statement to name wins.
This is done via checking the _id of HasIds during autonaming and only
applying a name if the HasId was created in the scope of autonaming.
There is no change to .autoSeed or .suggestName behavior.
Behavior of chisel3-plugins from before this change is maintained.
* Update docs with naming plugin changes
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This is a refinement of the assertion added in #1616 then removed in
#1654. Because Records now set the refs of children upon binding,
later, unbound Records could incorrectly override the refs. The first
set should win.
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It causes issues for some legal (if awkward) patterns. A larger refactor
of when refs are set could reinstate this check.
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This requires a combination of things, but it happens to be a
combination used by Diplomacy in Rocket Chip. It must be a Record in
compatibility code with Vecs as fields and a mix of components with and
without set directions.
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* Bugfix - module name collision for injecting aspect
* Fixed mechanism to avoid module name collisions
* Added comments for reviewer feedback
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Added forcename transform and tests
* Added documentation and additional error checking
* Added mdoc. Added RunFirrtlTransform trait
* Removed TODO comment
* Addressed reviewer feedback
* Removed trailing comma
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Use Data refs for name prefixing with aggregate elements
Vecs set the refs of their elements upon construction of those elements.
In the past, Records haven't set their elements refs until module close,
but it can be done sooner. Doing it upon binding means that refs will at
least be available for Records used in hardware elements. Since only
bound Data can be connected to anyway, Aggregate elements being
connected to will always have a ref which we can then use for creating
naming prefixes.
* Add tighter correctness checks
* Handle more cases in connection prefixing
Add support for forcing setRef to override a previous setting. This
is only used by BlackBox ports which need to drop their io prefix.
Also add a Try() around Data.bindingToString which sometimes throws
exceptions when being used to .toString a Data in an error message.
* Strip trailing spaces in names in compiler plugin
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* Fix `-e` option causing ChiselStage.emit* to error
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Add test of `-e` ChiselStage behavior
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Add test of `-e` ChiselStage behavior
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* Return 0.U for asUInt of a zero-element Seq
Add a condition to SeqUtils.asUInt to have it return an unspecified
width 0.U when applied to an empty sequence. This enables the ability
to do a Cat of a zero-element sequence.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Test elaboration of Cat on zero-element Seq
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Package chisel3 was not properly marked as an internal package so source
locators in reported errors would point to files like Bits.scala.
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* ExtModule's lacked support built in support for providing
the verilog source. This changes creates traits that
can be used with ExtModule to provide the support currently found in
BlackBox
- Add support for ExtModule helpers
- HasExtModuleResource to use addResource
- HasExtModuleInline to use setInline
- HasExtModulePath to use addPath
- Add tests of the above support.
- Note: These tests use Stage instead of Driver
- Added ScalaDoc for HasBlackBoxInline#setInline
* Fix the danged trailing commas.
* Change to use `.transform` as the correct API for `ChiselStage`
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Fixes #1606
Previously, the Data itself would be put on the prefix stack and its
full name would be used as the prefix for subsequent names. This meant
that prefixes would grow quadratically as the prefix is present both on
the Data pushed to the stack, and on the stack itself. This is fixed by
just using the "local" name of the Data being pushed on the stack.
A related issue is deferring the name resolution. This led to unintuitive
behavior when the name of a Data used as a prefix is overridden later
(usually when the Data is a return value). The overriding name would
show up in prefixes twice instead of once. It is much more intuitive to
grab the name at the moment of the connection creating the prefix rather
than deferring to later.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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Co-authored-by: Megan Wachs <megan@sifive.com>
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* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package
* Revert reg naming behavior (omit underscore)
* Added documentation and a test
* Addressed reviewer feedback.
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Test all cases in ParameterizedOneHotTesters
Co-authored-by: Jack Koenig <koenig@sifive.com>
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ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it
is Unserializable. Also the --chisel-output-file is added to the
ChiselCli.
New phase AddSerializationAnnotations constructs a
CircuitSerializationAnnotation from ChiselCircuitAnnotation and
ChiselOutputFileAnnotation. Both .fir and .pb file formats are
supported. Default format is .fir unless a --chisel-output-file is
specified with a .pb extension.
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* fix loadMemoryFromFile to work with binary
Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation
* Added test for binary format support in loadMemoryFromFile
* Added test for binary format support in loadMemoryFromFile
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It shouldn't be removed until we also remove the underlying chisel3.Driver.
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ChiselStage$ helpers (#1566)
* Add ChiselPhase
* Use ChiselPhase in ChiselStage, remove targets
Switch from a one-off PhaseManager inside ChiselStage to actually
using the newly added ChiselPhase. This removes the targets
method (and API) from ChiselStage.
* Stop writing to files in ChiselStage$ methods
Change the ChiselStage companion object methods, elaborate and
convert, to not write files. Under the hood, these are switched from
using ChiselStage (which, like all phases, will write files) to using
ChiselPhase.
* Test that ChiselStage$ methods write no files
Modify existing ChiselStage object method tests to check that no files
are written.
* Expand ChiselStage$ API with more helpers
This adds additional methods to the ChiselStage object for going
directly from a Chisel module to a string including: CHIRRTL, high
FIRRTL IR, Verilog, and SystemVerilog.
Differing from their ChiselStage class counterparts, these take no
arguments other than the module and write no files.
* Add tests of new ChiselStage$ helper methods
* Use ChiselStage object in tests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Remove usages of the deprecated trait PreservesAll and use an explicit
false invalidates. Additionally, all phases are converted to be more
canonical in there specification of dependencies by:
1. Overriding all default dependency implementations
2. Using def instead of val
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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