Enable Cat of Zero Element Vec (#1623)

* Return 0.U for asUInt of a zero-element Seq

Add a condition to SeqUtils.asUInt to have it return an unspecified
width 0.U when applied to an empty sequence. This enables the ability
to do a Cat of a zero-element sequence.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Test elaboration of Cat on zero-element Seq

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

2 files changed, 35 insertions, 0 deletions

diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index 793a5463..3369eb18 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -25,6 +25,7 @@ object Cat {
     * in the sequence forms the least significant bits.
     *
     * Equivalent to r(0) ## r(1) ## ... ## r(n-1).
+    * @note This returns a `0.U` if applied to a zero-element `Vec`.
     */
   def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
 }
diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala
new file mode 100644
index 00000000..2e52fe63
--- /dev/null
+++ b/src/test/scala/chiselTests/util/CatSpec.scala
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Cat
+
+import chiselTests.ChiselFlatSpec
+
+object CatSpec {
+
+  class JackIsATypeSystemGod extends MultiIOModule {
+    val in  = IO(Input (Vec(0, UInt(8.W))))
+    val out = IO(Output(UInt(8.W)))
+
+    out := Cat(in)
+  }
+
+}
+
+class CatSpec extends ChiselFlatSpec {
+
+  import CatSpec._
+
+  behavior of "util.Cat"
+
+  it should "not fail to elaborate a zero-element Vec" in {
+
+    ChiselStage.elaborate(new JackIsATypeSystemGod)
+
+  }
+
+}