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AgeCommit message (Expand)Author
2021-09-23make all verification statements publically available (#2089)Kevin Laeufer
2021-09-21implement trace API. (#2077)Jiuyang Liu
2021-09-15Fix higher-kinded types for autoclonetype (#2121)Adam Izraelevitz
2021-09-06Fix #2112, handle `?->1` caseBoyang Han
2021-09-06Test case reworkBoyang Han
2021-09-06Add a test case to demonstrate the bug found in #2112Boyang Han
2021-09-05Add Definition and Instance API (#2045)Adam Izraelevitz
2021-08-31Fix chisel3 <> for compatibility Bundles (Take 3) (#2093)Jack Koenig
2021-08-26add new APIs to BitPat (#2076)Jiuyang Liu
2021-08-25replace custom model checker with chiseltest formal verify command (#2075)Kevin Laeufer
2021-08-23Use BufferedCustomFileEmission in CircuitSerializationAnnotationJack Koenig
2021-08-23Emit .fir lazily, overcomes JVM 2 GiB String limitJack Koenig
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
2021-08-23Add multiple dimensions to VecInit fill and iterate (#2065)anniej-sifive
2021-08-21Update ChiselStage.scala (#2082)Ruige Lee
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. (#1944)"...Jack Koenig
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
2021-08-12Add DataView (#1955)Jack Koenig
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-08-04Added VecInit factory methods (fill,iterate) (#2059)anniej-sifive
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
2021-07-28Bundles can no longer be instantiated with bound hardware (#2046)Jared Barocsi
2021-07-14Fix Cat rename signal (#2011)Leway Colin
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
2021-07-09Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)Jack Koenig
2021-07-08Make it legal for concrete resets to drive abstract reset (#2018)Jack Koenig
2021-07-08Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023)Jack Koenig
2021-07-08Add `isOneOf` method to `ChiselEnum` (#1966)Verneri Hirvonen
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
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