getVerilog in Chisel3 (#1921)

2 files changed, 28 insertions, 0 deletions

diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala
new file mode 100644
index 00000000..a91444de
--- /dev/null
+++ b/src/main/scala/chisel3/verilog.scala
@@ -0,0 +1,15 @@
+package chisel3
+
+import chisel3.stage.ChiselStage
+import firrtl.AnnotationSeq
+
+object getVerilogString {
+  def apply(gen: => RawModule): String = ChiselStage.emitVerilog(gen)
+}
+
+object emitVerilog {
+  def apply(gen: => RawModule, args: Array[String] = Array.empty,
+                  annotations: AnnotationSeq = Seq.empty): Unit = {
+    (new ChiselStage).emitVerilog(gen, args, annotations)
+  }
+}
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index bc9c524a..7703e876 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -8,6 +8,8 @@ import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage, NoRunFirrtlCompile
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.Unserializable
 
+import scala.io.Source
+
 class SimpleIO extends Bundle {
   val in  = Input(UInt(32.W))
   val out = Output(UInt(32.W))
@@ -187,4 +189,15 @@ class ModuleSpec extends ChiselPropSpec with Utils {
     }
     ChiselStage.elaborate(new RawModule with Foo)
   }
+
+  property("getVerilogString(new PlusOne() should produce a valid Verilog string") {
+    val s = getVerilogString(new PlusOne())
+    assert(s.contains("assign io_out = io_in + 32'h1"))
+  }
+
+  property("emitVerilog((new PlusOne()..) shall produce a valid Verilog file in a subfolder") {
+   emitVerilog(new PlusOne(), Array("--target-dir", "generated"))
+    val s = Source.fromFile("generated/PlusOne.v").mkString("")
+    assert(s.contains("assign io_out = io_in + 32'h1"))
+  }
 }