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AgeCommit message (Expand)Author
2019-07-18Support Analog DontCare bulk-connect (#1056)Richard Lin
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
2019-06-24Changed Value macro in ChiselEnum so that it doesn't use deprecated (#1104)Hasan Genc
2019-06-11Added documentation to Decoupled, Conditionals, Counter (#1015)Adam Izraelevitz
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
2019-05-22Add toAnnotations method to ChiselExecutionOptionsSchuyler Eldridge
2019-05-22Add Driver Compatibility LayerSchuyler Eldridge
2019-05-22Add chisel3.stage.ChiselStageSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.MaybeFirrtlStageSchuyler Eldridge
2019-05-22Add stage.phases.AddImplicitOutputAnnotationFileSchuyler Eldridge
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
2019-05-22Add chisel3.stage.ChiselOptionsSchuyler Eldridge
2019-05-22Add chisel3.stage.ChiselCliSchuyler Eldridge
2019-05-22Add chisel3.stage AnnotationsSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13RawModule with no reset should be able to use withClock method. (#1065)Chick Markley
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
2019-05-12Cleanup loadMemoryFromFile documentationSchuyler Eldridge
2019-05-10Change LFSR16 deprecation from 3.3 -> 3.2Schuyler Eldridge
2019-05-10Augment LFSR16 test to test the enable as wellAndrew Waterman
2019-05-10Fix LFSR regressionAndrew Waterman
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
2019-05-09Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)Jack Koenig
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
2019-05-09Add Lfsr testsSchuyler Eldridge
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
2019-05-08Genericize LFSR testing infrastructureSchuyler Eldridge
2019-05-05Expand upon ScalaDoc in Driveredwardcwang
2019-05-01Make asTypeOf work for bundles with zero-width fields. (#1079)Paul Rigge
2019-04-26Bundle literals implementation (#1057)Richard Lin
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2019-04-19Fix wrong directionality for Vec(Flipped())Edward Wang
2019-04-15Avoid silently truncating BigInt to IntAndrew Waterman
2019-04-12Implement connectFromBits in ChiselEnum (#1052)Jack Koenig
2019-04-01Detect bundle aliasing (#1050)Richard Lin
2019-03-29Ignore empty aggregates elements when binding aggregate direction (#946)Jack Koenig
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Fix enum annotations (#936)Hasan Genc
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
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