diff options
| author | Schuyler Eldridge | 2019-01-30 12:06:00 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-05-22 16:17:17 -0400 |
| commit | 4c48d5a94f9242f471e4c1ad39c664c672eafe13 (patch) | |
| tree | da2a9526e01dacbeef7b8450c4974d4d6d06f414 /src | |
| parent | f447c2253081f7c2ede0658d059bc00c184312f9 (diff) | |
Add chisel3.stage.phases.Elaborate Phase
This adds an Elaborate Phase that expands ChiselGeneratorAnnotations
into ChiselCircuitAnnotations and deletes the original.
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/stage/phases/Elaborate.scala | 42 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala | 46 |
2 files changed, 88 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala new file mode 100644 index 00000000..0b0d71fb --- /dev/null +++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala @@ -0,0 +1,42 @@ +// See LICENSE for license details. + +package chisel3.stage.phases + +import java.io.{PrintWriter, StringWriter} + +import chisel3.ChiselException +import chisel3.internal.ErrorLog +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOptions} +import firrtl.AnnotationSeq +import firrtl.options.Viewer.view +import firrtl.options.{OptionsException, Phase} + +/** Elaborate all [[chisel3.stage.ChiselGeneratorAnnotation]]s into [[chisel3.stage.ChiselCircuitAnnotation]]s. + */ +class Elaborate extends Phase { + + /** + * @todo Change this to print to STDERR (`Console.err.println`) + */ + def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap { + case a: ChiselGeneratorAnnotation => + try { + Some(a.elaborate) + } catch { + case e: OptionsException => throw e + case e: ChiselException => + val copts = view[ChiselOptions](annotations) + val stackTrace = if (!copts.printFullStackTrace) { + e.chiselStackTrace + } else { + val s = new StringWriter + e.printStackTrace(new PrintWriter(s)) + s.toString + } + Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) + Some(a) + } + case a => Some(a) + } + +} diff --git a/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala b/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala new file mode 100644 index 00000000..4d99b24c --- /dev/null +++ b/src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala @@ -0,0 +1,46 @@ +// See LICENSE for license details. + +package chiselTests.stage.phases + +import org.scalatest.{FlatSpec, Matchers} + +import chisel3._ +import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation} +import chisel3.stage.phases.Elaborate + +import firrtl.options.Phase + +class ElaborateSpec extends FlatSpec with Matchers { + + class Foo extends Module { + override def desiredName: String = "Foo" + val io = IO( + new Bundle { + val in = Input(Bool()) + val out = Output(Bool()) + }) + + io.out := ~io.in + } + + class Bar extends Foo { + override def desiredName: String = "Bar" + } + + class Fixture { val phase: Phase = new Elaborate } + + behavior of classOf[Elaborate].toString + + it should "expand ChiselGeneratorAnnotations into ChiselCircuitAnnotations and delete originals" in new Fixture { + val annotations = Seq( ChiselGeneratorAnnotation(() => new Foo), + ChiselGeneratorAnnotation(() => new Bar) ) + val out = phase.transform(annotations) + + info("original annotations removed") + out.collect{ case a: ChiselGeneratorAnnotation => a } should be (empty) + + info("circuits created with the expected names") + out.collect{ case a: ChiselCircuitAnnotation => a.circuit.name } should be (Seq("Foo", "Bar")) + } + +} |
