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Add Cookbook tests
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Merge with master and support checking for failure with an explicit assertion message.
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This was originally mixed in with #199, Add Assert Data.
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Code that imports Chisel._ shouldn't see them.
Not sure if requireIOWrap is the right condition... or if cyan is a
good choice of color for deprecation warnings.
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Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
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firrtlDirection should only be used for emitting firrtl. Any checks on the actual direction should use the bound Direction `dir`.
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Scaladocs for utils
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These tests are intended to be the examples in the Chisel3 Wiki Cookbook.
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Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
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In the Chisel frontend, the implicit clock is named clock, but in the
generated FIRRTL, it is named clk. There is no reason for this
discrepancy, and yet fixing it is painful, as it will break test harnesses.
Better to take the pain now than later.
Resolves #258.
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o explain why this merge is necessary,
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constructor
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Add IrrevocableIO subclass of DecoupledIO that promises not to change .bits on a cycle after .valid is high and .ready is low
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Printable was using HasId.instanceName to get full names of Chisel nodes.
instanceName uses the parent module of the HasId to get the Component to use in
calling fullName on the underlying Ref. Unfortunately this means that any
reference to a port of a instance will leave off the instance name. Fixing this
required the following:
- Add Component argument to Printable.unpack so that we can call Arg.fullName
directly in the Printable
- Pass the currently emitting module as the Component to Printable.unpack in
the Emitter
- Remove ability to create FullName Printables from Modules since the Module
name is not known until after the printf is already emitted
This commit also updates the PrintableSpec test to check that FullName and
Decimal printing work on ports of instances
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Printable is a new type that changes how printing of Chisel types is represented
It uses an ordered collection rather than a format string and specifiers
Features:
- Custom String Interpolator for Scala-like printf
- String-like manipulation of "hardware strings" for custom pretty-printing
- Default pretty-printing for Chisel data types
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Eliminate builder compileOptions.
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Remove references to the Chisel package in favor of explicit chisel3 imports in tests,
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for io ports.
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Import chisel3.NotStrict.CompileOptions in Chisel package.
Add CompileOptions tests.
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signalName -> instanceName
SignalId -> InstanceId
Based on Stephen's comments on PR
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Removed extraneous logic
Renamed doStuff to buildAnnotatedCircuit
Removed println's
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generation of annotations in a chisel circuit that could be used by custom firrtl passes
This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
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* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
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Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
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