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2018-09-07Put do_* methods in SourceInfoTransformMacro groupSchuyler Eldridge
This places all do_* methods (and two unary methods in SInt and FixedPoint that act like do_* methods) inside the ScalaDoc group "SourceInfoTransformMacro". Classes/objects which need information about this group have an additional bare trait mixed in, `SourceInfoDoc`, that provides information about the group and its priority. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-31Support for verilog memory loading. (#840)Chick Markley
* Ability to load memories at simulation startup * first pass * create annotation * create skeleton Transform * Work in progress Building out transform and pass now * Support for LoadMemory annotation * Creates chisel and firrtl LoadMemory annotations * LoadMemoryTransform converts annotation into BlackBox InLine * Simple test that verilog bound modules get created. * Support for LoadMemory annotation * Supports Bundled/multi-field memories * more tests * support for `$readmemh` and `$readmemb` * warns if suffix used in file specification. * Support for LoadMemory annotation * Use standard chisel annotation idiom * Support for LoadMemory annotation * Fixes for @seldridge nits and super-nits * Support for LoadMemory annotation - transform now only runs if emitter is an instance of VerilogEmitter - suffixes on memory text files are now respected - if suffix exists and memory is aggregate, aggregate sub-fields will now be inserted before suffix - every bind module created gets a unique number - this is required when multiple loaded memories appear in a module - this should be generalized for other uses of binding modules * Support for LoadMemory annotation - remove un-needed suffix test * Support for LoadMemory annotation - remove instance walk, now just processes each module * Support for LoadMemory annotation - Move LoadMemoryTransformation into Firrtl for treadle to access it. * Support for LoadMemory annotation - One more bug in suffix handling has been eliminated * Support for LoadMemory annotation - remove unused findModule per jackkoenig - fixed complex test, bad filename edge case * Support for LoadMemory annotation - changed to not use intellij style column alignment for : declarations * Load memory from file Fixes based on @jkoenig review - remove unused BindPrefixFactory - Moved code from CreateBindableMemoryLoaders into to LoadMemoryTransfrom - Made map to find relevant memory annotations faster - Made map to find modules referenced by annotations faster - Made things private that should be private - DefAnnotatedMemorys are no longer referenced, shouldn't be found here. - println of error changed to failed * Loading memories from files - Many changes based on review - move stuff into experimental - clean up annotation manipulation - manage tests better - use more standard practices for transform * Loading memories from files - More review changes - Move doc from annotation to the object apply method that generates the annotation - Make scalastyle directives more specific - Use more efficient collect to generate name to module map - Made lines obey style length limit - a couple of cleanups of imports in tests - removed some commented out code - optimized checking for lines using .exists - use _ for unused variable in match
2018-08-29Inhibit aggressive resource file name mangling. (#884)Jim Lawson
* Inhibit aggressive resource file name mangling. This addresses #883. * Use common method to write resources to a directory to keep file names consistent.
2018-08-23Add FlattenInstance APISchuyler Eldridge
This adds a new trait, FlattenInstance, to chisel3.util.experimental. When mixed into a module or a specific instance this trait will "flatten", i.e., "inline that module and all of its submodules". This includes testing (additions to InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-23Add InlineInstance APISchuyler Eldridge
This adds a new trait, InlineInstance, to chisel3.util.experimental. This trait, when mixed into a specific module or instance, will "inline" that module, i.e., "collapse a module while preserving it's submodules." This includes testing (InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
We can sometimes shim with other workarounds like VecInit or manually creating a mux
2018-08-22Use a mix-in to override Seq errorEdward Wang
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
This adds an annotator that provides a linkage to the FIRRTL WiringTransform. This enables synthesizable cross module references between one source and multiple sinks without changing IO (the WiringTransform bores through the hierarchy). Per WiringTransform, this will connect sources to their closest sinks (as determined by BFS) or fail if ownership is indeterminate. Make TesterDriver.execute work like Driver.execute: - annotations are included when running FIRRTL - custom transforms are run automatically Also, add a bore method to BoringUtils that allows you to do one source to multi-sink mapping in a single call. This adds a test that this is doing the same thing as the equivalent call via disjoint addSink/addSource. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
Fixes #852
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
See https://github.com/freechipsproject/chisel3/issues/867 for future API discussion
2018-07-19Add support for Input() and Output() (available in Chisel2 since ↵Jim Lawson
ucb-bar/chisel2-deprecated#734) and test for same.
2018-07-10Fix use of read-only refs on rhs of connect in compatibility mode (#854)Jack Koenig
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
They should not be deprecated until zero-width wires actually work
2018-07-04Add test that UInt, SInt, and FP literals do not impact namingJack Koenig
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBitsducky
2018-07-04Style fixesducky
2018-07-04properly fix undefined clock/reset issuesducky
2018-07-04Add BundleLiteralSpecRichard Lin
2018-07-04Comment out assertion test, fix ref generationRichard Lin
2018-07-04Add new test LitInsideOutsideTesterchick
This shows errors comparing literals
2018-07-04unbrokenducky
2018-07-04brokenducky
2018-07-04delete debugging stuffducky
2018-07-04lol=(Richard Lin
2018-07-04bundle literal mockup, but broken =(Richard Lin
2018-07-04work on new style literal accessorsducky
2018-07-02Direct to FIRRTL (#829)Jack Koenig
Provide direct conversion from ChiselIR to FIRRTL. Provide Driver support for dumping ProtoBuf.
2018-06-29Catch returns from within when blocks and provide an error message (#842)Jack Koenig
Resolves #841
2018-06-25Correcting documentation errors in Arbiter.scala (#839)Brendan Sweeney
Documentation for example had parameters in wrong order, and was missing @param. Additionally, it was lacking a module wrapper. This has been corrected.
2018-06-20Programmatic Port Creation (#833)Jack Koenig
Add chisel3.experimental.IO for programmatic port creation in Raw and MultiIOModules. suggestName is required to name ports that cannot be named by reflection. Two ports cannot be given the same name.
2018-06-18Fixed UIntToOH(x, 1) invocation with x.width == 0 (#778)Wesley W. Terpstra
2018-06-01Literals set their ref so they no longer get named (#826)Jack Koenig
Fixes #763 Add tests for #763 and #472 This has a few implications * Constructing a literal no longer increments _T_ suffixes * Internally, wrapping a literal Bits in Node(...) will work * Literal Bools work in withReset/withClockAndReset
2018-05-24Fix UIntToOH for output widths larger than 2^(input width) (#823)Andrew Waterman
* Add test for UIntToOH * Pad UIntToOH inputs to support oversized output widthds * Optimize Bits.pad in case of known widths * Add missing import and fix test in OneHotMuxSpec
2018-05-23Add test for zero-width Mems. (#821)grebe
2018-04-22Add Module.currentModule for getting a reference to the current Module (#810)Jack Koenig
Resolves #809
2018-03-23Fallback null insertion for autoclonetype (#801)Richard Lin
If autoclonetype is unable to determine an outer class, this attempts to insert a null (and give a deprecation warning), preserving old behavior (in some cases) where the new behavior doesn't work. This doesn't provide full compatibility with old autoclonetype: this does not attempt null insertion in the general first argument (if it's not an outer class reference). Reasoning is that inserting a null for an explicit argument is probably not the right thing to do, and will likely cause a difficult-to-debug NullPointerException (whereas that would be unlikely for an outer class, which is not always referenced in Bundle subclass code).
2018-03-06Fix SyncReadMem.read; add test (#796)Andrew Waterman
SyncReadMem.read with an enable signal currently only works in compatibility mode, where Wires are implicitly initialized to DontCare. Fix by explicitly assigning DontCare to the Wire. This might fix #775.
2018-03-02Fix for 792 (#793)Richard Lin
Makes Builder.updateBundleStack a bit stricter in deciding how many stack frames to discard by additionally matching against method names and deleting stack frames at or above the frame currently being inserted.
2018-02-28Refactor Annotations (#767)Jack Koenig
* Generalize ChiselAnnotation This allows us to delay creation of Annotations till elaboration is complete. Also update all annotation-related code. * Add RunFirrtlTransform Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old ChiselAnnotation (now called ChiselLegacyAnnotation) * Use unique test directories in ChiselRunners.compile
2018-02-28Auto Clone Bundles in Companion Objects (#788)Richard Lin
2018-02-21Support zero-entry queues (but not for irrevocable) (#780)Andrew Waterman
2018-02-20Make Bundle abstract (#774)Jack Koenig
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