diff options
| author | Jack Koenig | 2018-07-03 13:30:31 -0700 |
|---|---|---|
| committer | Richard Lin | 2018-07-04 18:39:28 -0500 |
| commit | ffb87e99c5c0c6c5864293092f942be33206de22 (patch) | |
| tree | 4b097126547be39dae6ac782c0f79adb46018b7c /src | |
| parent | 94bde13444b956b2ef3c3cf7e94870b1d890f65d (diff) | |
Add test that UInt, SInt, and FP literals do not impact naming
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/chiselTests/BetterNamingTests.scala | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index 41b8eef3..03abb7dc 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -76,4 +76,17 @@ class BetterNamingTests extends ChiselFlatSpec { elaborate { module = new DigitFieldNamesInRecord; module } assert(module.getNameFailures() == Nil) } + + "Literals" should "not impact temporary name suffixes" in { + class MyModule(withLits: Boolean) extends Module { + val io = IO(new Bundle {}) + if (withLits) { + List(8.U, -3.S, 1.25.F(2.BP)) + } + WireInit(3.U) + } + val withLits = chisel3.Driver.emit(() => new MyModule(true)) + val noLits = chisel3.Driver.emit(() => new MyModule(false)) + withLits should equal (noLits) + } } |
