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2022-08-16Add OpaqueType support to Records (backport #2662) (#2679)mergify[bot]
* Add OpaqueType support to Records (#2662) OpaqueTypes are essentially type aliases that hide the underlying type. They are implemented in Chisel as Records of a single, unnamed element where the wrapping Record does not exist in the emitted FIRRTL. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit df5afee2d41b5bcd82d4013b977965c0dfe046fd) * Fix test compilation * Fix OpaqueType tests in RecordSpec Need to implement cloneType correctly and to warn instead of error when accessing .toTarget of non-hardware types because that is a warning (not error) in 3.5. * Waive MiMa false positives Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-15Printables for verification preconditions (backport #2663) (#2680)mergify[bot]
* Printables for verification preconditions (#2663) Add support for printable within assert and assume verification statements Co-authored-by: Girish Pai <girish.pai@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 7df5653309b5e48e1732b335610d9a7e8449f903) * Waive MiMa false positive Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-13Add option to treat warnings as errors (backport #2676) (#2677)mergify[bot]
* Add option to treat warnings as errors (#2676) Add --warnings-as-errors option (cherry picked from commit 498946663726955c380a1e420f5d7b9630000aad) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/aop/injecting/InjectingAspect.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/package.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala * Resolve backport conflicts Co-authored-by: Zachary Yedidia <zyedidia@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-12Show equivalent warnings/errors only once (#2673) (#2675)mergify[bot]
(cherry picked from commit ae76ff4cb303a6646e48dc044be47051b67e7cbb) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-08-12Add ability to suppress enum cast warnings (#2671) (#2674)mergify[bot]
(cherry picked from commit 1ad820f7f549eddcd7188b737f59a240e48a7f0a) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-08-02Remove remaining chiselNames (#2635) (#2656)mergify[bot]
(cherry picked from commit 8538269a14e0d5a1163298a79aa43b77a380aabc) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-28Implement DecoupledIO.map utility (#2646) (#2649)mergify[bot]
(cherry picked from commit b20df1d6cda03f6eef28ee480e0aade914c5face) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-21Deprecate chiselName and NoChiselNamePrefix trait (#2627) (#2633)mergify[bot]
Also remove all non-testing uses of chiselName. (cherry picked from commit 1c5d1b5317a0c9fe7ef9d15138065a817380a1e4) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-143.5x: Make explicit copy constructors for ExplicitCompileOptions (#2629)Megan Wachs
* Add copy constructors for compile options * Add tests for the copy constructors Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-07-13New enhanced API for specifying Chisel to Firrtl Annotations (#2628) (#2631)mergify[bot]
(cherry picked from commit 4b10cf7a276e90b280c1fd57070566acac3d80d3) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-07-08CompileOptions: add and use emitStrictConnects (#2622) (#2623)mergify[bot]
(cherry picked from commit 11e8cc60d6268301cff352b8a1d7c4d672b5be11) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-07-06Refactor TruthTable.apply and add factory method for Espresso (backport ↵mergify[bot]
#2612) (#2620) * Refactor TruthTable.apply and add factory method for Espresso (#2612) Improves performance of creating TruthTables by processing entire BitPats rather than individual bits. New TruthTable factory method enables constructing TruthTables with semantics of OR-ing output BitPats together rather than erroring when multiple terms have the same input BitPat. This alternative factory method matches semantics for the output format of Espresso. Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 231f14e74f112a9f721e774561126b2bd1250039) # Conflicts: # src/main/scala/chisel3/util/BitPat.scala * Resolve backport conflicts Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-07-06Implement trait for Chisel compiler to name arbitrary non-Data types (#2610) ↵mergify[bot]
(#2617) Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 3ab34cddd8b87c22d5fc31020f10ddb2f1990d51) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-27Deprecate TransitName (backport #2603) (#2606)mergify[bot]
* Deprecate TransitName (#2603) * Deprecate TransitName * Add @nowarn macros to usages of TransitName in the repo Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit a0b05190e5303ec28a0c7abe645d81e9a72023ff) * Update src/main/scala/chisel3/util/Valid.scala * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs <megan@sifive.com>
2022-06-23Add DataMirror isIO, isReg, isWire (#2601) (#2602)mergify[bot]
(cherry picked from commit 7fa0d8bf1cafcdf141046476a100abf021bdcac4) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-06-22Pass optional name in ImportDefinitionAnno (#2592) (#2594)mergify[bot]
Used for separate elaboration of Definition and Instance (cherry picked from commit 48d57cc8db6f38fdf0e23b7dce36caa404c871b8) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-06-18Handle varargs constructor arguments in Bundle plugin (#2585) (#2588)mergify[bot]
Previously, the plugin would crash with a useless internal error. (cherry picked from commit 9fcfb252beb9f06d8d1409fe7db9c8b3b6b962ce) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-16Define leading '_' as API for creating temporaries (backport #2580) (#2581)mergify[bot]
* Define leading '_' as API for creating temporaries Chisel and FIRRTL have long used signals with names beginning with an underscore as an API to specify that the name does not really matter. Tools like Verilator follow a similar convention and exclude signals with underscore names from waveform dumps by default. With the introduction of compiler-plugin prefixing in Chisel 3.4, the convention remained but was hard for users to use unless the unnnamed signal existed outside of any prefix domain. Notably, unnamed signals are most useful when creating wires inside of utility methods which almost always results in the signal ending up with a prefix. With this commit, Chisel explicitly recognizes signals whos val names start with an underscore and preserve that underscore regardless of any prefixing. Chisel will also ignore such underscores when generating prefixes based on the temporary signal, preventing accidental double underscores in the names of signals that are prefixed by the temporary. (cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6) * Remove unused defaultPrefix argument from _computeName (cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala * Resolve backport conflicts * Waive false positive binary compatibility errors Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-13Add ImplicitInvalidate, to help migrate the explicitInvalidate compiler ↵mergify[bot]
option (#2575) (#2579) * Added ImplicitInvalidate trait with tests (cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-11Micro-optimize BitPat.rawString (#2577) (#2578)mergify[bot]
BitPat.rawString is called a lot when decoding and is used for certain BitPat operations. We should use it less but this is at least a bandaid. (cherry picked from commit c11af20fe5b211ec72ba00f3ce0880d7933e566b) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-08Added migration for inferModuleReset (#2571) (#2573)mergify[bot]
Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-07Add single argument Bits.extract (#2566) (#2568)mergify[bot]
(cherry picked from commit 255c56c3955a8c16191a6751e7d547cfcfd96705) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-06Add --warn:reflective-naming (backport #2561) (#2565)mergify[bot]
* Factor buildName into reusable function The new function is chisel3.internal.buildName. (cherry picked from commit 370ca8ac68f6d888dd99e1b9e63f0371add398cf) * Add --warn:reflective-naming This new argument (and associated annotation) will turn on a warning whenever reflective naming changes the name of a signal. This is provided to help migrate from Chisel 3.5 to 3.6 since reflective naming is removed in Chisel 3.6. (cherry picked from commit 97afd9b9a1155fa7cd5cedf19f9e0c15fbe899ec) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-03Deprecate implicit .U() and .S() syntax for literal bit extracts (backport ↵mergify[bot]
#2534) (#2559) * Deprecate .U() and .S() syntax for literal bit extracts (#2534) (cherry picked from commit cadaf33a650ef898fdab2f81244e4ad6a07a9ea8) # Conflicts: # macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala * Fix backport conflict (#2560) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-02Support VerificationStatement in the naming plugin (#2555) (#2557)mergify[bot]
Previously, verification statements (assert, assume, cover, and printf) were only named via reflection. (cherry picked from commit 7fa2691f670813eef4ec59fc27c4e4f625d598de) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-01Add formatted Printable interpolator `cf` (#2528) (#2553)mergify[bot]
This is a formatted version of the p"..." interpolator analogous to Scala's f"..." interpolator. The primary difference is that it supports formatting interpolated variables by following the variable with "%<specifier>". For example: printf(cf"myWire = $myWire%x\n") This will format the hardware value "myWire" as a hexidecimal value in the emitted Verilog. Note that literal "%" must be escaped as "%%". Scala types and format specifiers are supported and are handled in the same manner as in standard Scala f"..." interpolators. (cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-05-29Deprecate accessing the name of non-hardware Data (#2550) (#2552)mergify[bot]
This includes (and is tested) for both the old .*Name APIs and .toTarget (cherry picked from commit 6e0d8d6b12e9d8f94c2cc43b92b2366ec70dfd50) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-27Make ExtModule port naming consistent with Module (#2548) (#2549)mergify[bot]
ExtModule now uses the same namePorts implementation as regular Modules. Previously, ExtModules only allowed port naming via runtime reflection. This meant that .suggestName and other naming APIs do not work. It also breaks FlatIO for ExtModule which is a potential replacement API for BlackBox's special `val io` handling. (cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-19Support := views to DontCare (#2536) (#2539)mergify[bot]
(cherry picked from commit 77a6c93592d5766d66f199720fc6d69478005091) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-14Deprecate named arguments for methods moving to macros in 3.6 (#2530)Jack Koenig
These methods will start using def macros and since def macros do not supported named arguments this will be a source-incompatible change. This deprecation will warn users that they need to remove any uses of named arguments on these methods.
2022-05-12Support separately elaborating definition and instance in ChiselStage ↵mergify[bot]
(backport #2512) (#2520) * Support separately elaborating definition and instance in ChiselStage (#2512) (cherry picked from commit a0aa4d1550e3fbde199a98529cffeb176fb4bed8) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/experimental/hierarchy/Instance.scala # core/src/main/scala/chisel3/internal/Builder.scala * fixing imports (#2522) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-04-25Fix error message for BlackBox without val io <: Record (#2504) (#2505)mergify[bot]
(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-20Generate a balanced tree with reduceTree (#2318) (#2499)mergify[bot]
The difference in logic depth for various paths now has a maximum of 1. Also make treeReduce order the same for 2.12 and 2.13 .grouped(_) returns an Iterator .toSeq on an Iterator returns a Stream in 2.12 and a List in 2.13 This can lead to changes in order when bumping from 2.12 to 2.13 that can be avoided by simply using an eager collection explicitly. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 6975f77f3325dec46c613552eac663c29011a67c) Co-authored-by: Martin Schoeberl <martin@jopdesign.com>
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
Fixes #2470 (cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-15Enable Clock Invalidation (#2485) (#2487)mergify[bot]
Loosen restrictions on clocks to enable them to be connected to DontCare, i.e., be invalidated. Co-authored-by: Jack Koenig <koenig@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 5d8a0c8e406376f7ceda91273fb0fa7a646865aa) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-04-12Enhance views to [sometimes] support dynamic indexing and implement FlatIO ↵mergify[bot]
(backport #2476) (#2479) * Capture 1:1 mappings of Aggregates inside of views This is implemented by including any corresponding Aggregates from the DataView.mapping in the AggregateViewBinding.childMap (which is now of type Map[Data, Data]). This enables dynamically indexing Vecs that are themselves elements of larger Aggregates in views when the corresponding element of the view is a Vec of the same type. It also increases the number of cases where a single Target can represent part of a view. (cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e) * Add FlatIO API for creating ports from Bundles without a prefix (cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb) * [docs] Add FlatIO to the general cookbook (cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-01Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468) (#2469)mergify[bot]
(cherry picked from commit 4da1e89f3a0b79adcb39ea5defb393ed6c00fa2f) Co-authored-by: fzi-hielscher <47524191+fzi-hielscher@users.noreply.github.com>
2022-03-25rm unused/deprecated BlackBoxResourceAnno import (#2458) (#2460)mergify[bot]
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 2c2d72ceaa494b6acc351ff4300dbb40d4a7d863) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-03-10Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)mergify[bot]
Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung <debs@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-09Support BlackBoxes in D/I (#2438) (#2442)mergify[bot]
Also delete an errant println in InstanceSpec (cherry picked from commit 3462c54c018a52a377f1c89121b6ed99c5b0ae1d) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-08Add scanLeftOr and scanRightOr utilies (#2407) (#2437)mergify[bot]
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 73d3c26029c07c17ce179dfead092eab4fb8ae2c) Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com>
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
* Issue errors on out-of-range extracts when width is known Firrtl will catch this later on, but better to error early if possible. * Test that errors are generated on OOB extracts when width is known (cherry picked from commit 462def429aa87becb544533880a3075a806c53e4) Co-authored-by: Andrew Waterman <andrew@sifive.com>
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
Widths are now padded to the maximum width of the inputs. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
(cherry picked from commit 024847d75079a125e5946e9dcf2ed9c14d2db730) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-02-08Overload getVerilogString to accept arguments (#2401) (#2402)mergify[bot]
(cherry picked from commit b55dc36d4edd1d22db37616235c003c89d68d29b) Co-authored-by: Carlos Eduardo <me@carlosedp.com>
2022-02-03FillInterleaved documentation: swap order of elements in Seq example (#2393) ↵mergify[bot]
(#2395) (cherry picked from commit 055a85298c46c6734880cd828af436adbded1d0a) Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com>
2022-02-01Improve error reporting (backport #2376) (#2379)mergify[bot]
* Improve error reporting (#2376) * Do not trim stack traces of exceptions with no stack trace This prevents us from accidentally giving stack traces to exceptions that don't have them and giving misleading messages telling users to use --full-stacktrace when it won't actually do anything. Also deprecate ChiselException.chiselStackTrace which is no longer being used anywhere in this codebase. * Add exception class for multiple-errors reported New chisel3.internal.Errors replaces old anonymous class that would show up as chisel3.internal.ErrorLog$$anon$1 in error messages. * Add new option --throw-on-first-error This tells Chisel not to aggregate recoverable errors but instead to throw an exception on the first one. This gives a stack trace for users who need it for debugging. (cherry picked from commit ff2e9c92247b3848659fa09fdd53ddde2120036a) * Waive MiMa false positives The waived change is to a package private constructor. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-02-01Optional clock param for memory ports (#2333) (#2382)mergify[bot]
Warn if clock at memory instantiation differs from clock bound at port creation and port clock is not manually passed Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 465805ec7b2696a985eaa12cf9c6868f11ac2931) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 17:14:59 +0000