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AgeCommit message (Expand)Author
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
2021-05-20Implement PLA (#1912)Jiuyang Liu
2021-05-20implement model checking API for chiseltest (#1910)Jiuyang Liu
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-27Introduce VecLiterals (#1834)Chick Markley
2021-04-21fixing context bug (#1874)Deborah Soung
2021-03-23Make plugin autoclonetype always on (#1826)Jack Koenig
2021-03-18Add toString method to BitPat (#1819)Boyang Han
2021-03-18Don't toggle top.cpp clock and reset on same cycle (#1820)Schuyler Eldridge
2021-03-17Fix incorrect usage of emitFirrtl in test (#1817)Schuyler Eldridge
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12[plugin] Disable BundleComponent by default, add option to enableJack Koenig
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
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