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2016-10-05Add sbt-buildinfo support.Jim Lawson
2016-10-04Add CompileOptions implicits to all Module constructors - fix #310. (#311)Jim Lawson
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
2016-09-23Merge branch 'master' into gsdtJim Lawson
2016-09-21Expose FIRRTL asClock constructAndrew Waterman
2016-09-15Merge branch 'master' into gsdtJim Lawson
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig
2016-09-06Verify we can suppress the inclusion of default compileOptions.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Make compileOptions in the Chisel package effective.Jim Lawson
2016-08-30Add example of specific CompileOptions settings to tests.Jim Lawson
2016-08-30Add abstract classes with explicit connection checking options.Jim Lawson
2016-08-29Check module-specific compile options.Jim Lawson
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-08-24Per Chisel meeting.chick
2016-08-21AnnotatingExample:chick
2016-08-21Add AnnotationSpec file which provides an example of a way to implement gener...chick
2016-08-21Add annotating example to test new signal name apichick
2016-08-16Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
2016-07-27More compatibility fixesJim Lawson
2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-27Additional compatibility code.Jim Lawson
2016-07-25Enable current (chisel2-style) compatibility mode.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-25Use more idiomatic ScalaTest exception expecting code.Jim Lawson
2016-07-25catch Bad connection exceptionJim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
2016-07-21Ensure test_wire is sinkable.Jim Lawson
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Generate better names for nodes (#190)Jack Koenig
2016-07-20Compile ok.Jim Lawson
2016-07-19Fix LitBinding and MultiAssign tests.Jim Lawson
2016-07-19Incorporate connection logic.Jim Lawson
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-07Don't check GCD result before sending it a requestAndrew Waterman
2016-06-21Most of the remaining tests with Module, IO wrapping.Jim Lawson
2016-06-21New Module, IO, Input/Output wrapping.Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-08Move utils into utilsducky
2016-06-08Rename Chisel -> chisel in testsducky
2016-06-01Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)Wesley W. Terpstra
2016-05-20Update BackendCompilationUtilities.verilogToCpp to specify top-modulejackkoenig
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