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AgeCommit message (Expand)Author
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
2019-02-19Add TransitNameSpecSchuyler Eldridge
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
2019-02-19Util doc lsfr (#1021)Chick Markley
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Define Data .toString (#985)Richard Lin
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
2018-12-19Fix width inferencing issue (#952)Jack Koenig
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-12-04Make toBools support chained applyJack Koenig
2018-11-26Trim Stack Trace (#931)Albert Chen
2018-11-20Make Vec cloneType keep directions of elements (#945)Jack Koenig
2018-11-01Add BigInt / Int to Bool conversion (0.B, 1.B) (#913)Richard Lin
2018-10-29Turn off strong enum annotations (#916)Hasan Genc
2018-10-25Check BaseModule.name for NullPointerExceptionSchuyler Eldridge
2018-10-25Make BaseModule.name lazySchuyler Eldridge
2018-10-12Strong enums (#892)Hasan Genc
2018-10-05Change InlineSpec to expect "_" and not "$"Schuyler Eldridge
2018-10-03Add DataMirror.modulePorts (#901)Richard Lin
2018-08-31Support for verilog memory loading. (#840)Chick Markley
2018-08-23Add FlattenInstance APISchuyler Eldridge
2018-08-23Add InlineInstance APISchuyler Eldridge
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
2018-08-22Use a mix-in to override Seq errorEdward Wang
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
2018-07-19Add support for Input() and Output() (available in Chisel2 since ucb-bar/chis...Jim Lawson
2018-07-10Fix use of read-only refs on rhs of connect in compatibility mode (#854)Jack Koenig
2018-07-04Add test that UInt, SInt, and FP literals do not impact namingJack Koenig
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBitsducky
2018-07-04Add BundleLiteralSpecRichard Lin
2018-07-04Comment out assertion test, fix ref generationRichard Lin
2018-07-04Add new test LitInsideOutsideTesterchick
2018-07-04unbrokenducky
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