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authorEdward Wang2018-08-21 18:36:13 -0700
committeredwardcwang2018-08-22 11:55:38 -0700
commit3491ba89859e4b45b557485025ffe8cf5e298b54 (patch)
treed3c089f62313993d7c20e3fbf78866c1a43d40fc /src/test
parentadfdebc920530199a3a4473b7a1230088fec3f5e (diff)
Implement varargs MixedVec API
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/chiselTests/MixedVecSpec.scala19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
index 271467aa..0e4cc3e7 100644
--- a/src/test/scala/chiselTests/MixedVecSpec.scala
+++ b/src/test/scala/chiselTests/MixedVecSpec.scala
@@ -159,6 +159,25 @@ class MixedVecSpec extends ChiselPropSpec {
implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
implicit val noShrinkInt = Shrink[Int](_ => Stream.empty)
+ property("MixedVec varargs API should work") {
+ assertTesterPasses {
+ new BasicTester {
+ val wire = Wire(MixedVec(UInt(1.W), UInt(8.W)))
+ wire(0) := 1.U
+ wire(1) := 101.U
+
+ chisel3.assert(wire(0) === 1.U)
+ chisel3.assert(wire(1) + 1.U === 102.U)
+
+ val wireInit = MixedVecInit(1.U, 101.U)
+ chisel3.assert(wireInit(0) === 1.U)
+ chisel3.assert(wireInit(1) + 1.U === 102.U)
+
+ stop()
+ }
+ }
+ }
+
property("MixedVecs should be assignable") {
forAll(safeUIntN(8)) { case (w: Int, v: List[Int]) =>
assertTesterPasses {