From 3491ba89859e4b45b557485025ffe8cf5e298b54 Mon Sep 17 00:00:00 2001
From: Edward Wang
Date: Tue, 21 Aug 2018 18:36:13 -0700
Subject: Implement varargs MixedVec API

---
 src/test/scala/chiselTests/MixedVecSpec.scala | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
index 271467aa..0e4cc3e7 100644
--- a/src/test/scala/chiselTests/MixedVecSpec.scala
+++ b/src/test/scala/chiselTests/MixedVecSpec.scala
@@ -159,6 +159,25 @@ class MixedVecSpec extends ChiselPropSpec {
   implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
   implicit val noShrinkInt = Shrink[Int](_ => Stream.empty)
 
+  property("MixedVec varargs API should work") {
+    assertTesterPasses {
+      new BasicTester {
+        val wire = Wire(MixedVec(UInt(1.W), UInt(8.W)))
+        wire(0) := 1.U
+        wire(1) := 101.U
+
+        chisel3.assert(wire(0) === 1.U)
+        chisel3.assert(wire(1) + 1.U === 102.U)
+
+        val wireInit = MixedVecInit(1.U, 101.U)
+        chisel3.assert(wireInit(0) === 1.U)
+        chisel3.assert(wireInit(1) + 1.U === 102.U)
+
+        stop()
+      }
+    }
+  }
+
   property("MixedVecs should be assignable") {
     forAll(safeUIntN(8)) { case (w: Int, v: List[Int]) =>
       assertTesterPasses {
-- 
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