chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2016-05-04	Multiple assign tester	ducky
	Closes #90
2016-05-04	Rewrite BlackBox IO contract, replace _clock\|_reset	Stephen Twigg
	The old blackbox behavior still emitted extmodules that have a clk, reset pin and prepended all io's with io_ (ultimately). Most verilog modules do not follow this distinction (or use a slightly different name for clock and so on). Thus, instead BlackBox has been rewritten to not assume a clk or reset pin. Instead, the io Bundle specified is flattened directly into the Module.ports declaration. The tests have been rewritten to compensate for this. Also, added a test that uses the clock pin. As a secondary change, the _clock and _reset module parameters were bad for two reasons. One, they used null as a default, which is a scala best practices violation. Two, they were just not good names. Instead the primary constructor has been rewritten to take an Option[Clock] called override_clock and an Option[Bool] called override_reset, which default to None. (Note how the getOrElse call down below is much more natural now.) However, users may not want to specify the Some(their_clock) so I also added secondary constructors that take parameters named clock and reset and wrap them into Some calls into the primary constructor. This is a better UX because now you can just stipulate clock=blah in instantiation of that module in symmetry with using the clock in the definition of the module by invoking clock. PS: We could also back out of allowing any overrides via the Module constructor and just require the instantiating Module to do submodule.clock := newclock, etc.
2016-04-26	Replace deprecated usage in tests. Issue #149	Jim Lawson

2016-04-18	Add whenever method to TblSpec forall to weed out invalid test values.	Jim Lawson

2016-04-15	Test FIRRTL string literals more aggressively	Andrew Waterman

2016-04-14	Disallow Counters with negative n	Andrew Waterman
	One could make an argument for disallowing n=0, too, but HW generators will benefit from our leniency. Closes #107. Thanks @jackkoenig
2016-03-18	Add test for assertions in modules with pipedlined reset	jackkoenig

2016-03-18	Only randomize directory names during testing	jackkoenig

2016-02-25	Fixed comment punctuation and made it clearer that using an init() method ↵	chick
	for DeqIO and EnqIO initialization is likely to change.
2016-02-24	Remove the assignment statements in EnqIO and DeqIO Bundle constructors.	chick
	Make the corresponding test run faster by giving it a Counter.
2016-02-24	Create a test that breaks because of assignment statements in DeqIO and ↵	chick
	EnqIO bundles
2016-02-22	Fixed improper apostrophe in it's in TesterDriverSpec comments	chick

2016-02-10	TesterDriverSpec is simpler and cleaner, extraneous circuit has been removed.	chick
	Cleanup comment for finish method in BasicTester, and finishWrapper in TesterDriver.
2016-02-10	The TesterDriverSpec has been made stronger by altering circuit in finish method	chick

2016-02-10	Added some comments describing potential use of the finish method hook	chick
	clean up the test example
2016-02-09	fixed test for finish method being put in the wrong place	chick

2016-02-09	Added support for finish method of BasicTester to be overridden in a ↵	chick
	subclass which allows tester to have clean up and other construction code executed after a user code executed during constructor of that subclass
2016-02-08	Added a simple tests that DeqIO and EnqIO get their directions right and are ↵	chick
	clonable
2016-01-30	Add BlackBox support and test, refactor execute => assertTesterPasses	ducky

2016-01-28	Fixed NoneOptionBundleTester to actually instantiate a module without an ↵	azidar
	input port
2016-01-28	Merge branch 'master' into modrefactor	Andrew Waterman

2016-01-28	Merge branch 'master' into scalastyle	Andrew Waterman

2016-01-27	Add unit test for module deduplication	ducky

2016-01-16	Add When test and fix when / elsewhen / otherwise behavior	ducky

2016-01-06	Don't silence legitimate warnings - these println()s should be controlled by ↵	Jim Lawson
	a diagnostic/debugging infrastructure.
2016-01-05	Scalastyle fixes - whitespace or comments only.	Jim Lawson

2015-12-11	Refactor tests to use stop() and assert() instead of io.error/io.done	ducky
	Gate assert, printf, stop by reset Fix testbenches that never worked Change simulation prints to display cycle at which test was signaled to end, not when simulator stops Better documentation for Counter
2015-12-11	Add stop() in BasicTester as a replacement for io.done	ducky

2015-12-11	Add support for printf and asserts, add testbench for asserts and printf	ducky

2015-12-11	Merge pull request #64 from ucb-bar/optionablebundle	Adam Izraelevitz
	Add Option support in Bundle
2015-12-10	Add Option support in Bundle	ducky

2015-12-09	Refactor testharness generation to create directories and have minimal API	ducky

2015-12-09	Extend TesterDriver to optionally take in additional Verilog sources	ducky

2015-12-06	Split internal and FIRRTL packages	ducky

2015-11-06	Merge pull request #59 from ucb-bar/testing-improvements	Jim Lawson
	Further testing improvements
2015-11-06	added elaboration tests for remaining old Chisel3 examples	Henry Cook

2015-11-06	Fixed bug that created Vec(Reg(...)) instead of Reg(Vec(...))	azidar

2015-11-06	Fix counter tests	Henry Cook

2015-11-04	Merge pull request #56 from ucb-bar/stylefix	Jim Lawson
	Style fixes for test code
2015-11-04	Style fixes for test code, so we can go back down to zero style errors for tests	ducky

2015-11-04	Fix Tbl.io	Henry Cook

2015-11-04	Use elaborate for elaboration tests, not execute	Henry Cook

2015-11-04	Supply smaller values for generatorDrivenConfig to reduce test time.	Henry Cook

2015-11-04	Remove Parameters library and refactor Driver.	Henry Cook
	In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances, this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester. The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed. Further work is needed on individual tests to use assertions instead of .io.error.
2015-10-23	Fix stylistic issues and document standard Chisel generators	ducky

2015-10-23	Add Scalaland unit tests for Reg	ducky

2015-10-23	Whitespace scalastyle fixes for tests	ducky

2015-08-14	more tests	Henry Cook

2015-08-14	VecShiftReg test	Henry Cook

2015-08-14	todo	Henry Cook