diff options
| author | Henry Cook | 2015-08-14 01:54:03 -0700 |
|---|---|---|
| committer | Henry Cook | 2015-08-14 01:54:03 -0700 |
| commit | f0a5bbdadedf08c80300ae861c76a1cb05611b80 (patch) | |
| tree | d7db27b06d52fdf614fe65818deedaa46338bcd5 /src/test | |
| parent | c23943b41de55de9af249a3b231558ad23fc8087 (diff) | |
todo
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 47e4af2c..e8f4f640 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -9,7 +9,7 @@ class VecSpec extends ChiselPropSpec { class ValueTester(w: Int, values: List[Int]) extends BasicTester { io.done := Bool(true) - val v = Vec(values.map(UInt(_, width = w))) + val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? io.error := v.zip(values).map { case(a,b) => a != UInt(b) }.foldLeft(UInt(0))(_##_) |