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2019-04-12Implement connectFromBits in ChiselEnum (#1052)Jack Koenig
This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf
2019-04-01Detect bundle aliasing (#1050)Richard Lin
2019-03-29Ignore empty aggregates elements when binding aggregate direction (#946)Jack Koenig
Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Fix enum annotations (#936)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
* Add HasBlackBoxPath trait * Use 'setResource' instead of 'addResource' * Add ScalaDoc
2019-02-19Add TransitNameSpecSchuyler Eldridge
This adds a test of chisel3.util.TransitName (which is used for the TransitName documentation). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
Close #1009
2019-02-19Util doc lsfr (#1021)Chick Markley
* Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Fixed typos in LFSR - Reduce trials a little - Add test of LFSR period * Update documentation for LSFR16 - Fixed remaining LSFR, arrgh - Removed intellij specific warning suppressor - Fixed comments/scaladoc wording and case. * Update documentation for LSFR16 - Use printable interpolator as example of printing out a Vec
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Define Data .toString (#985)Richard Lin
toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
This adds two tests to the BoringUtilsSpec to explicitly verify that deduplication is required when boring. This adds tests that both verify that the test passes as expected with deduplication enabled and that the same test fails with deduplication disabled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
Verilator 4.008 dropped the hammer on procedural wire assignment to align with the IEEE standard (first I've heard of this, though). The VerilogVendingMachine.v test resource will error in Verilator 4.008 with a PROCASSWIRE error if you try to compile it. This fixes that example to only assign to a register. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-12-19Fix width inferencing issue (#952)Jack Koenig
* Fix width propagation of non-literals in WireInit and RegInit * Change .getWidth to throw an exception instead of calling .get * Add utilities for checking inferred vs. known widths * Add tests for Wire, WireInit, Reg, and RegInit width inference * Add ScalaDoc for Reg, Wire, RegInit, and WireInit
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-12-04Make toBools support chained applyJack Koenig
The expanded version substituted in by the macro was misspelled, renamed from toBools -> do_toBools as expected by the macro
2018-11-26Trim Stack Trace (#931)Albert Chen
- Trim stack trace to show better, reduced information to the user - Add --full-stacktrace to FIRRTL option to show full stack trace
2018-11-20Make Vec cloneType keep directions of elements (#945)Jack Koenig
Fixes #893
2018-11-01Add BigInt / Int to Bool conversion (0.B, 1.B) (#913)Richard Lin
2018-10-29Turn off strong enum annotations (#916)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Ignore annotation tests using ScalaTest's 'ignore', rather than by commenting them out
2018-10-25Check BaseModule.name for NullPointerExceptionSchuyler Eldridge
This wraps the evaluation of BaseModule.name in try/catch to look for a NullPointerException that may result from trying to evaluate desiredName before it's ready. This catches a test case of using a desiredName that depends on a later defined eager subinstance. h/t @jackkoenig Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-25Make BaseModule.name lazySchuyler Eldridge
This changes BaseModule.name to be lazy (instead of eager) to enable a desiredName to be a function of a sub-instance. This includes a test case showing the new behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-12Strong enums (#892)Hasan Genc
* Added new strongly-typed enum construct called "StrongEnum". "StrongEnum" will automatically generate annotations that HDL backends can use to mark components as enums Removed "override val width" constructor parameter from "Element" so that classes with variable widths, like the new strong enums, can inherit from it Changed the parameter types of certain functions, such as "switch", "is", and "LitArg.bindLitArg" from "Bits" to "Element", so that they can take the new strong enums as arguments * Added tests for the new strong enums * Changed StrongEnum exception names and made sure in StrongEnum tests that the correct types of exceptions are thrown * Fixed bug where an enum's global annotation would not be set if it was used in multiple circuits Made styling changes to StrongEnum.scala * Reverted accidental changes to the AnnotatingDiamond test * Changed the API for casting non-literal UInts to enums Added an isValid function that checks whether or not enums have valid values Calling getWidth on an enum's companion object now returns a BigInt instead of an Int * Casting a literal to an enum using the StrongEnum.castFromNonLit(n) function is now simply a wrapper for StrongEnum.apply(n) * Fixed compilation bug * * Added "next" method to EnumType * Renamed "castFromNonLit" to "fromBits" * The FSM example in the test/scala/cookbook now uses StrongEnums * * Changed strong enum API, so that users no longer have to declare both a class and a companion object for each strong enum * Strong enums do not have to be static any longer * * Added scope protections to ChiselEnum.Value so that users cannot call it outside of a ChiselEnum definition * Renamed ChiselEnum.Value type to ChiselEnum.Type so that we can give it a companion object just like UInt and Bool do * * Moved strong enums into experimental package * Non-literal UInts can now be cast to enums with apply() rather than fromBits() * Reduced code-duplication by moving some functions from EnumType and Bits to Element
2018-10-05Change InlineSpec to expect "_" and not "$"Schuyler Eldridge
A FIRRTL change to inlining changes the inlined instance delimiter to "_" from "$". This change is reflected here in an update to the associated Chisel tests for the Inline API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-03Add DataMirror.modulePorts (#901)Richard Lin
2018-08-31Support for verilog memory loading. (#840)Chick Markley
* Ability to load memories at simulation startup * first pass * create annotation * create skeleton Transform * Work in progress Building out transform and pass now * Support for LoadMemory annotation * Creates chisel and firrtl LoadMemory annotations * LoadMemoryTransform converts annotation into BlackBox InLine * Simple test that verilog bound modules get created. * Support for LoadMemory annotation * Supports Bundled/multi-field memories * more tests * support for `$readmemh` and `$readmemb` * warns if suffix used in file specification. * Support for LoadMemory annotation * Use standard chisel annotation idiom * Support for LoadMemory annotation * Fixes for @seldridge nits and super-nits * Support for LoadMemory annotation - transform now only runs if emitter is an instance of VerilogEmitter - suffixes on memory text files are now respected - if suffix exists and memory is aggregate, aggregate sub-fields will now be inserted before suffix - every bind module created gets a unique number - this is required when multiple loaded memories appear in a module - this should be generalized for other uses of binding modules * Support for LoadMemory annotation - remove un-needed suffix test * Support for LoadMemory annotation - remove instance walk, now just processes each module * Support for LoadMemory annotation - Move LoadMemoryTransformation into Firrtl for treadle to access it. * Support for LoadMemory annotation - One more bug in suffix handling has been eliminated * Support for LoadMemory annotation - remove unused findModule per jackkoenig - fixed complex test, bad filename edge case * Support for LoadMemory annotation - changed to not use intellij style column alignment for : declarations * Load memory from file Fixes based on @jkoenig review - remove unused BindPrefixFactory - Moved code from CreateBindableMemoryLoaders into to LoadMemoryTransfrom - Made map to find relevant memory annotations faster - Made map to find modules referenced by annotations faster - Made things private that should be private - DefAnnotatedMemorys are no longer referenced, shouldn't be found here. - println of error changed to failed * Loading memories from files - Many changes based on review - move stuff into experimental - clean up annotation manipulation - manage tests better - use more standard practices for transform * Loading memories from files - More review changes - Move doc from annotation to the object apply method that generates the annotation - Make scalastyle directives more specific - Use more efficient collect to generate name to module map - Made lines obey style length limit - a couple of cleanups of imports in tests - removed some commented out code - optimized checking for lines using .exists - use _ for unused variable in match
2018-08-23Add FlattenInstance APISchuyler Eldridge
This adds a new trait, FlattenInstance, to chisel3.util.experimental. When mixed into a module or a specific instance this trait will "flatten", i.e., "inline that module and all of its submodules". This includes testing (additions to InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-23Add InlineInstance APISchuyler Eldridge
This adds a new trait, InlineInstance, to chisel3.util.experimental. This trait, when mixed into a specific module or instance, will "inline" that module, i.e., "collapse a module while preserving it's submodules." This includes testing (InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
We can sometimes shim with other workarounds like VecInit or manually creating a mux
2018-08-22Use a mix-in to override Seq errorEdward Wang
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
This adds an annotator that provides a linkage to the FIRRTL WiringTransform. This enables synthesizable cross module references between one source and multiple sinks without changing IO (the WiringTransform bores through the hierarchy). Per WiringTransform, this will connect sources to their closest sinks (as determined by BFS) or fail if ownership is indeterminate. Make TesterDriver.execute work like Driver.execute: - annotations are included when running FIRRTL - custom transforms are run automatically Also, add a bore method to BoringUtils that allows you to do one source to multi-sink mapping in a single call. This adds a test that this is doing the same thing as the equivalent call via disjoint addSink/addSource. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
Fixes #852
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
See https://github.com/freechipsproject/chisel3/issues/867 for future API discussion
2018-07-19Add support for Input() and Output() (available in Chisel2 since ↵Jim Lawson
ucb-bar/chisel2-deprecated#734) and test for same.
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