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2020-03-24Propagate user compile options for Chisel.Module (#1387)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-24Add ChiselStageSpec for string/circuit emissionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-23Add NoChiselNamePrefix to ignore instances in @chiselName (#1383)Jack Koenig
Add trait chisel3.experimental.NoChiselNamePrefix which causes @chiselName to skip naming of the instance effectively preventing it from prefixing any vals inside the instance. It can be applied to classes such that all instances of that class have this property, or to individual instances (via creating an anonymous class inline). Also add basic ScalaDoc for NoChiselNamePrefix and chiselName.
2020-03-19Test nested ChiselException in ChiselMainSchuyler Eldridge
Adds two tests: 1. Test that an internal requirement failure (a bare exception) inside a Builder is properly reported/trimmed by ChsielStage/ChiselMain 2. Test that the full stack trace includes the ChiselException Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-11Wrap elaboration in ChiselExceptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Wrap elaboration in ChiselException
2020-03-06Provide API to set concrete type of implicit reset (#1361)Jack Koenig
Introduces mutually-exclusive traits RequireAsyncReset and RequireSyncReset to set the type of the implicit reset in MultiIOModules. The Scala-type remains Reset, but the Chisel elaboration-time checks apply. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-02Cleanup aspects (#1359)Adam Izraelevitz
* Clean up aspects * Refactored InjectingAspect with InjectorAspect * Made AspectLibrary work with objects * Cleaned up code * Apply suggestions from code review * Added tests, removed deprecated newInstance call * Backed out removal of newInstance as exceptions were different * Removed trailing commas
2020-02-12Fix := of Reset and AsyncReset to DontCare (#1336)Jack Koenig
2020-02-10Make Queue.irrevocable work properly in chisel3Edward Wang
Close #1134
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
* Add support for readUnderWrite to SyncReadMem * Add write collision behavior test to MemorySpec * Update constant names
2020-01-31Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-21Merge branch 'master' into big-decimal-methods-for-num-typeschick
# Conflicts: # src/test/scala/chiselTests/IntervalSpec.scala
2020-01-21Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-21Removed unnecessary castChick Markley
Non-functional, must have been a typo
2020-01-21Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-21Merge branch 'master' into fix-bitpat-whitespaceJim Lawson
2020-01-17Bugfix: Select.instances now works with blackboxes (#1303)Adam Izraelevitz
2020-01-07Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-07Merge branch 'master' into fix-bitpat-whitespaceJim Lawson
2019-12-18Add method asBool to Clock.chick
Shortcut for .asUInt.asBool Added test to show it works
2019-12-18- New trait HasBinaryPoint which provides literal values as double and big ↵chick
decimal - made .F and .I work for creating fixed point and interval lits from big decimal - Added NumObject trait which provides new math conversions - Made a Num object that extends NumObject - Add this trait to FixedPoint and Interval for backward compatibility - Removed code that is now in NumObject, keeping things DRY - Add tests to FixedPointSpec to show lit conversion to double and big decimal - Add tests to IntervalSpec to show lit conversion to double and big decimal - Add tests to LiteralExtractorSpec to show general math conversions between BigInts with binary points and double and big decimal
2019-12-18BitPat supports whitespace and underscores, presumably for human readability.chick
The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069
2019-12-12Fixed problem creating Interval literals with full rangeschick
- boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail
2019-12-11- add simple test of IntervalRange helperschick
- getLowestPossibleValue - getHighestPossibleValue - getPossibleValues
2019-12-06Revert "Compat compile options macro (#1253)" (#1268)Jack Koenig
This reverts commit 85fe90d5b7ed4e1101b0b3959a1d362eb93915ac.
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Compat compile options macro (#1253)Jack Koenig
* Use macro to materialize CompileOptions in Chisel._ This switches from using an implicit val that required awkward suppression (as illustrated in CompileOptionsSpec) to allowing overriding in the same way as done in "import chisel3._" via the creation of an implicit val in lexical scope. * Deprecate Chisel.defaultCompileOptions
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-05Add tests for exhaustive MuxLookup optimizationAlbert Magyar
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
Accomplished by changing the code gen for casting literals to aggregates. Rather than connecting the literal to a wire that is then bit selected from, just bit select from the literal which saves the creation of an intermediate wire and matches FIRRTL's semantics for legal async reset initial values.
2019-11-02Tests for anonymous/class-in-module desiredNameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Add BoringUtils.bore test for internal boringSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
Plan to be released with 3.3. Breaks experimental Range API. Adds new Interval type and associated support. This commit adds the following: - Renamed Range to IntervalRange to avoid name collision with scala Range - Changed RangeTransform macro to Return an IntervalRange - Improved error messages on missing comma or decimal - Added notational support for binary point - Some formatting cleanup also - SIntFactory - Change to use IntervalRange API - UIntFactory - UInt from range has custom width computation - It does not need to deal with lowerbound extending bit requirements - Code to handle special case of range"[0,0]" to have a width of 1 - IR.scala - Removed Bound and other constraint code that was duplicating firrtl stuff - Added new RangeType - Added IntervalRange class and object - RangeSpec - modified just a bit to handle notational differences - previous range interpolator returned tuple now returns IntervalRange - Add IntervalType to emitter - Added IntervalSpec with many tests - Added ScalaIntervalSimulatorSpec which tests golden model for Interval - Added ScalaIntervalSimulator which is a golden model for Interval - This gold may not have been polished to a high sheen - Add IntervalLit cases to Converter - Add Interval PrimOps to IR - asInterval, wrap, squz, clip, setp, decp, incp - Add IntervalLit class to IR - Add Interval to MonoConnect - Add Interval Type to Bits (in experimental package) - add conversions to Interval from other types - Add Interval clone stuff to Data - Add Literal creation helpers to chisel3 package - these may move to experimental if I can figure that out
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
Dynamically indexing a Vec of Flipped bidirectional Bundles would get the wrong directions on the elements of the Bundles Fixes #1192
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
* Add a tree reduce function to Vec * Change function names of reduce operation function in Vec * Change reference to single layer operation in Vec.reduce * Commint name change for pair macro * Remove pair, call not necessary and can just be used from grouped(2) and map * Changed to reduceTree, added default identity function for single reduce. * Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style * Cleanup Vec initialization, implicitCompileOptions
2019-09-13Fix Queue.apply for size 0 in chisel3._ code (#1177)Jack Koenig
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
* Move dontTouch out of experimental package. * Move RawModule, MultiIOModule out of experimental. * Respond to comments - Move LagacyModule from experimental to internal. *NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions. * Fix up a few more imports.
2019-08-27Test stack trace trimming for ChiselStageSchuyler Eldridge
Use FIRRTL stage-style testing to check stdout printing without and with --full-stacktrace. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add test that stack trace trimming worksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add firrtlTests.Utils methodsSchuyler Eldridge
This adds methods for examining stdout/stderr and exit codes inside of a Scala program. This are pulled directly from firrtlTests, but we aren't currently publishing those anywhere that we can get at them. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-13Add support for asynchronous reset (#1011)Jack Koenig
Adds new AsyncReset and "abstract" Reset types. Reset is inferred in FIRRTL to be either AsyncReset or Bool. The "reset type" of a register is set by the type of its reset signal: val asyncReset: AsyncReset = IO(Input(AsyncReset())) val syncReset: Bool = IO(Input(Bool())) val abstractReset: Reset = IO(Input(Reset())) val asyncReg = withReset(asyncReset) { RegInit(0.U) } val syncReg = withReset(syncReset) { RegInit(0.U) } val inferredReg = withReset(abstractReset) { RegInit(0.U) } AsyncReset can be cast to and from Bool. Whereas synchronous reset is equivalent to a mux in front of a flip-flop and thus can be driven by logic, asynchronous reset requires that the reset value is a constant. This is checked in FIRRTL. Inference of the concrete type of a Reset occurs based on the type the Reset's drivers. This inference is very simple, it is simple forward propagation of the type, but it allows for writing blocks and modules that are agnostic to the reset type. In particular, the implicit `reset` value in MultiIOModule and thus Module is now concretely an instance of Reset and thus will be inferred in FIRRTL.
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
2019-08-08Require target is hardware for Vec.apply(a: UInt)Schuyler Eldridge
Adds a check that a Vec being indexed by a UInt is, in fact, a hardware type. This includes a test for this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add SInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add UInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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