diff options
| author | Schuyler Eldridge | 2019-09-12 12:03:40 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-10-21 12:04:16 -0400 |
| commit | 22434659d8ac8a7855c7d7c00c7adf71e8e1099b (patch) | |
| tree | e8208ae30e34131e8c2722784cb62a6c8300fe43 /src/test | |
| parent | 54f68516404d2d40a79c6a2f8dbb70ed7016d147 (diff) | |
Add BoringUtils.bore test for internal boring
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/BoringUtilsSpec.scala | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala index 856f6b91..755ba60b 100644 --- a/src/test/scala/chiselTests/BoringUtilsSpec.scala +++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala @@ -106,4 +106,21 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { .getMessage should startWith ("Unable to determine source mapping for sink") } + class InternalBore extends RawModule { + val in = IO(Input(Bool())) + val out = IO(Output(Bool())) + out := false.B + BoringUtils.bore(in, Seq(out)) + } + + class InternalBoreTester extends ShouldntAssertTester { + val dut = Module(new InternalBore) + dut.in := true.B + chisel3.assert(dut.out === true.B) + } + + it should "work for an internal (same module) BoringUtils.bore" in { + runTester(new InternalBoreTester) should be (true) + } + } |
