summaryrefslogtreecommitdiff
path: root/src/test
AgeCommit message (Expand)Author
2021-07-09Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)Jack Koenig
2021-07-08Make it legal for concrete resets to drive abstract reset (#2018)Jack Koenig
2021-07-08Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023)Jack Koenig
2021-07-08Add `isOneOf` method to `ChiselEnum` (#1966)Verneri Hirvonen
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
2021-05-20Implement PLA (#1912)Jiuyang Liu
2021-05-20implement model checking API for chiseltest (#1910)Jiuyang Liu
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-27Introduce VecLiterals (#1834)Chick Markley
2021-04-21fixing context bug (#1874)Deborah Soung
2021-03-23Make plugin autoclonetype always on (#1826)Jack Koenig
2021-03-18Add toString method to BitPat (#1819)Boyang Han
2021-03-17Fix incorrect usage of emitFirrtl in test (#1817)Schuyler Eldridge
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12[plugin] Disable BundleComponent by default, add option to enableJack Koenig
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
2021-02-09Make it possible to GC Data instancesJack Koenig
2021-02-09Add no-plugin-tests for testing Chisel without the compiler pluginJack Koenig
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
2021-01-21Remove val ioJack Koenig
2021-01-21Rename MultiIOModule to ModuleJack Koenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 17:49:32 +0000