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Also change Data.outerModule to Bundle._outerInst since it is only used
in autoclonetype. _outerInst is also Option[Object] instead of
Option[BaseModule] because the outer object could also be a Bundle.
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Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705
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Prevents DontCare from affecting type inference
Fixes #728
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Fixes #708
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Make InvalidateAPI emit to a test directory
Add *.swp and test_run_dir to .gitignore
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Fixes #482
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Closes #729
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Also enforce switch is conditions are mutually exclusive literals
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Use DontCare on `outs` not `ins` in InvalidateAPISpec.
Add additional InvalidateAPISpec tests demonstrating selective override of Strict/NotStrict behavior.
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* Require explicit connection to DontCare to generate "is invalid".
* Add tests for RefNotInitializedException.
Currently, we fail the when ... otherwise ...
* Disable ScalaTest shrinking on error in ComplexAssignSpec.
* fix broken merge; still some binding issues
* cleanup DontCare connection checks; add missing directions to test module IOs
* Have library code inherit compileOptions from the enclosing Module (if it exists).
* work around current firrtl uninitialized references with Strict compile options and explicitInvalidate
* more CompileOptions cleanup; move test-specific defines to package object
* minimize differences with master
* set default CompileOptions.explicitInvalidate to false until we fix the FIRRTL when issue
* ignore the StrictCompiler property checks (until CompileOptions.explicitInvalidate is defaulted to true)
* Revert "more CompileOptions cleanup; move test-specific defines to package object"
This reverts commit e4486edcba990d150e76e08a2fc6abca033556e0.
* Revert "work around current firrtl uninitialized references with Strict compile options and explicitInvalidate"
This reverts commit 426faa430a62c3dac2dbdf33044d3386d4243157.
* remove unused code
* Convert to binding-based DontCare implementation
* comment cleanup to minimize differences with master
* Tentatively remove possibly redundant DefInvalid on module ports.
* Respond to code review change request.
- backout build.sbt change
- correct indentation
- handle bulk of DontCare semantics in elemConnect()
- have DontCare extend Element, not Data (eliminate most Object specific methods
- add comments indicating reason for explicit DontCare connections
* Initialize test elements without requiring a DontCare.
* Respond to review change requests.
- DontCare should work on left or right side in BiDirectional connections
- call bind() to set DontCare binding instead of messing with internal variables
- DontCares are only equivalent with DontCares
- clean up processWhens() definition
* Eliminate DontCare connection to inputs in MonoConnect().
* Pull aggregates apart for the purpose of DontCare connections.
* Restore the explicit (conditionally executed) ports DefInvalidin ImplicitModule()
* Don't add DontCare's to the module list of _ids.
* Add missing DefInvalid() to LegacyModule().
* Respond to review requests: add DontCare BiConnect Vec, remove null parent hack to avoid addId(), initialize singletons early in Builder
* Move DontCare out of chisel3.experimental.
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Addresses #419
cloneType is now marked (through comments only) as an internal API.
chiselCloneType deprecated (and changed to cloneTypeFull internally, analogous to cloneTypeWidth).
chiselTypeOf(data) introduced as the external API to get a chisel type from a hardware object
Intended usage: cloning is an implementation detail, and chisel types and hardware objects both should act as immutable types, with operations like Input(...), Reg(...), etc returning a copy and leaving the original unchanged. Hence, the clone operations are all deprecated.
Deletes what appears to be an unused Bundle companion object.
Input(...), Output(...), Flipped(...) require the object to be unbound
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Preprocess chisel3 IR before emission to determing whether
whens have alternatives.
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Rest of the binding refactor
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Bool implements Reset. Compatibility package includes an implicit
conversion from Reset to Bool.
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No functional changes
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* Fix style of literal creators
Literal creators for UInt, SInt and Bool were declared with parens, but
virtually all uses of these methods do not use parens. This is for
issue #539.
This fix is an API breaking change. If anyone has used parens, e.g.
val x = 1.U()
This will now be an error
* remove trailing parens from literal creators in IntegerMathTester
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Part 1 of mega-change in #578
Major notes:
- Input(...) and Output(...) now (effectively) recursively override their elements' directions
- Nodes given userDirection (Input, Output, Flip - what the user assigned to _that_ node) and actualDirection (Input, Output, None, but also Bidirectional and BidirectionalFlip for mostly Aggregates), because of the above (since a higher-level Input(...) can override the locally specified user direction).
- DataMirror (node reflection APIs) added to chisel3.experimental. This provides ways to query the user given direction of a node as well as the actual direction.
- checkSynthesizable replaced with requireIsHardware and requireIsChiselType and made available in chisel3.experimental.
Internal changes notes:
- toType moved into Emitter, this makes the implementation cleaner especially considering that Vec types can't be flipped in FIRRTL. This also more clearly separates Chisel frontend from FIRRTL emission.
- Direction separated from Bindings, both are now fields in Data, and all nodes are given hierarchical directions (Aggregates may be Bidirectional). The actualDirection at the Element (leaf) level should be the same as binding directions previously.
- Bindings are hierarchical, children (of a, for example, Bundle) have a ChildBinding that points to their parent. This is different than the previous scheme where Bindings only applied at the Element (leaf) level.
- Lots of small misc clean up.
Future PRs will address other parts of #578, including stricter direction checks that aren't a side-effect of this internal refactor, stricter checks and splitting of binding operations (Wire vs. WireInit), and node operations not introduced here (getType and deprecation of chiselCloneType). Since those shouldn't mess with internals, those should be much smaller.
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bump scoverage version
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Replace ambiguous bi-connect ("<>") with mono-connect (":=") for internal Pipe wiring.
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Fixes #495
Helps distinguish between Records/Bundles defined in Chisel._ vs.
chisel3._. Also override compilationOptions when bulk connecting
Records/Bundles defined in Chisel._. This allows Records/Bundles defined
in Chisel._ code to be correctly bulk connected in chisel3._ code.
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* Partially revert 8e4ddc62db448b613ae327792e72defca4d115d4
It was an incomplete fix for handling Vec(0).
* Fix assignment from 0-entry Vec: add test
375e2b6a0a456c55298d82837d28986de6211ebc introduced a regression for bundles
containing zero-entry Vecs. Until zero-width UInts are supported, the
zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on
a bundle. Undoing that commit's replacement of Data.flatten with
Aggregate.getElements is the best interim fix.
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* still trying to find right mix
* Making some progress on Mux1H
* Mux1H that works in non-optimzed fashion for FixedPoint, works pretty well in general
Catches some additional problem edge cases
Some tests that illustrate most of this
* Moved in Angie's code for handling FixedPoint case
Cleaned up tests considerably, per @ducky64 review
* Just a bit more cleanup
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Fixes #554
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Using the sample_element of the created wire is incorrect because Wires have no
direction so the Wire constructed for a Vec of Module IO was constructed
incorrectly. Fixes #569 and resolves #522.
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Make it relatively easy to override a single CompileOption.
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Fixes #567
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This caused one hot muxing problems in dsptools
FixedPoint spec fixed based on error uncovered by this change
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This also allows asUInt/asTypeOf to work properly on those Bundles,
even though zero-width wire support is lacking.
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Use fold(0) instead of reduce to handle the corner case.
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Allow muxing FxP of different widths and BPs
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* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)"
This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2.
This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality.
* Add missing implicits to Vec.apply() signature.
* Use correct macro (CompileOptionsTransform) for indexWhere.
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