Use input element to decide if Vec of values has direction (#570)

Using the sample_element of the created wire is incorrect because Wires have no
direction so the Wire constructed for a Vec of Module IO was constructed
incorrectly. Fixes #569 and resolves #522.

1 files changed, 40 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 438cf515..2ece7c88 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -147,6 +147,42 @@ class ZeroEntryVecTester extends BasicTester {
   stop()
 }
 
+class PassthroughModuleIO extends Bundle {
+  val in = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
+}
+
+class PassthroughModule extends Module {
+  val io = IO(new PassthroughModuleIO)
+  io.out := io.in
+}
+
+class PassthroughModuleTester extends Module {
+  val io = IO(Flipped(new PassthroughModuleIO))
+  // This drives the input of a PassthroughModule
+  io.in := 123.U
+  assert(io.out === 123.U)
+}
+
+
+class ModuleIODynamicIndexTester(n: Int) extends BasicTester {
+  val duts = Vec.fill(n)(Module(new PassthroughModule).io)
+  val tester = Module(new PassthroughModuleTester)
+
+  val (cycle, done) = Counter(true.B, n)
+  for ((m, i) <- duts.zipWithIndex) {
+    when (cycle =/= i.U) {
+      m.in := 0.U  // default
+      assert(m.out === 0.U)
+    }
+  }
+  // only connect one dut per cycle
+  duts(cycle) <> tester.io
+  assert(duts(cycle).out === 123.U)
+
+  when (done) { stop() }
+}
+
 class VecSpec extends ChiselPropSpec {
   // Disable shrinking on error.
   implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -204,4 +240,8 @@ class VecSpec extends ChiselPropSpec {
   property("A Vec with zero entries should compile and have zero width") {
     assertTesterPasses{ new ZeroEntryVecTester }
   }
+
+  property("Dynamic indexing of a Vec of Module IOs should work") {
+    assertTesterPasses{ new ModuleIODynamicIndexTester(4) }
+  }
 }