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authorJim Lawson2017-05-25 09:03:25 -0700
committerGitHub2017-05-25 09:03:25 -0700
commit0d121a2e357511e9e7d975ae5f2d316e47cbf43b (patch)
tree533691f828b87eb4e700400d7ec88c4d0b5bfd81 /src/test/scala
parentcb28230d50475428f432b2906dd5246e27f3a687 (diff)
Update internal Pipe wiring - fixes #615" (#616)
Replace ambiguous bi-connect ("<>") with mono-connect (":=") for internal Pipe wiring.
Diffstat (limited to 'src/test/scala')
-rw-r--r--src/test/scala/chiselTests/ConnectSpec.scala16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/ConnectSpec.scala b/src/test/scala/chiselTests/ConnectSpec.scala
index 30e23f55..fb0675c4 100644
--- a/src/test/scala/chiselTests/ConnectSpec.scala
+++ b/src/test/scala/chiselTests/ConnectSpec.scala
@@ -3,7 +3,7 @@
package chiselTests
import chisel3._
-import chisel3.experimental.{FixedPoint, Analog}
+import chisel3.experimental.{Analog, FixedPoint}
import chisel3.testers.BasicTester
abstract class CrossCheck extends Bundle {
@@ -19,6 +19,17 @@ class CrossConnects(inType: Data, outType: Data) extends Module {
io.out := io.in
}
+class PipeInternalWires extends Module {
+ import chisel3.util.Pipe
+ val io = IO(new Bundle {
+ val a = Input(Bool())
+ val b = Input(UInt(32.W))
+ })
+ val pipe = Module(new Pipe(UInt(32.W), 32))
+ pipe.io.enq.valid <> io.a
+ pipe.io.enq.bits <> io.b
+}
+
class CrossConnectTester(inType: Data, outType: Data) extends BasicTester {
val dut = Module(new CrossConnects(inType, outType))
stop()
@@ -82,4 +93,7 @@ class ConnectSpec extends ChiselPropSpec {
property("SInt := Analog should fail") {
intercept[ChiselException]{ new CrossConnectTester(SInt(16.W), Analog(16.W)) }
}
+ property("Pipe internal connections should succeed") {
+ elaborate( new PipeInternalWires)
+ }
}