| Age | Commit message (Expand) | Author |
|---|
| 2019-01-25 | WireDefault instead of WireInit, keep WireInit around (#986) | Martin Schoeberl |
| 2019-01-22 | Define Data .toString (#985) | Richard Lin |
| 2019-01-22 | Fix BoringUtilsSpec to require no dedup | Schuyler Eldridge |
| 2019-01-22 | Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943) | Albert Magyar |
| 2019-01-21 | Support DontCare in Mux and cloneSupertype (#995) | Richard Lin |
| 2019-01-11 | Add test for chiselNaming of Seq[Data] | Andrew Waterman |
| 2018-12-19 | Fix width inferencing issue (#952) | Jack Koenig |
| 2018-12-04 | Add asBool, deprecate toBool | Jack Koenig |
| 2018-12-04 | Add asBools, deprecate toBools | Jack Koenig |
| 2018-12-04 | Make toBools support chained apply | Jack Koenig |
| 2018-11-26 | Trim Stack Trace (#931) | Albert Chen |
| 2018-11-20 | Make Vec cloneType keep directions of elements (#945) | Jack Koenig |
| 2018-11-01 | Add BigInt / Int to Bool conversion (0.B, 1.B) (#913) | Richard Lin |
| 2018-10-29 | Turn off strong enum annotations (#916) | Hasan Genc |
| 2018-10-25 | Check BaseModule.name for NullPointerException | Schuyler Eldridge |
| 2018-10-25 | Make BaseModule.name lazy | Schuyler Eldridge |
| 2018-10-12 | Strong enums (#892) | Hasan Genc |
| 2018-10-05 | Change InlineSpec to expect "_" and not "$" | Schuyler Eldridge |
| 2018-10-03 | Add DataMirror.modulePorts (#901) | Richard Lin |
| 2018-08-31 | Support for verilog memory loading. (#840) | Chick Markley |
| 2018-08-23 | Add FlattenInstance API | Schuyler Eldridge |
| 2018-08-23 | Add InlineInstance API | Schuyler Eldridge |
| 2018-08-22 | Implement varargs MixedVec API | Edward Wang |
| 2018-08-22 | Make MixedVec wire init consistent with VecInit | Edward Wang |
| 2018-08-22 | Remove dynamic indexing for now | Edward Wang |
| 2018-08-22 | Use a mix-in to override Seq error | Edward Wang |
| 2018-08-22 | MixedVec: clarify dynamic indexing of heterogeneous elements | Edward Wang |
| 2018-08-22 | Warn user that using Seq for hardware construction in Bundle is not supported | Edward Wang |
| 2018-08-22 | MixedVec implementation | Edward Wang |
| 2018-08-07 | BoringUtils / Synthesizable Cross Module References (#718) | Schuyler Eldridge |
| 2018-07-31 | Cleanup implicit conversions (#868) | Jack Koenig |
| 2018-07-31 | Ensure names work for bundles and literals. (#853) | Jim Lawson |
| 2018-07-31 | Revert removal of bit extraction const prop for literals (#857) | Jack Koenig |
| 2018-07-19 | Add support for Input() and Output() (available in Chisel2 since ucb-bar/chis... | Jim Lawson |
| 2018-07-10 | Fix use of read-only refs on rhs of connect in compatibility mode (#854) | Jack Koenig |
| 2018-07-04 | Add test that UInt, SInt, and FP literals do not impact naming | Jack Koenig |
| 2018-07-04 | Prefer litValue, eliminate litToBigInt | ducky |
| 2018-07-04 | Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBits | ducky |
| 2018-07-04 | Add BundleLiteralSpec | Richard Lin |
| 2018-07-04 | Comment out assertion test, fix ref generation | Richard Lin |
| 2018-07-04 | Add new test LitInsideOutsideTester | chick |
| 2018-07-04 | unbroken | ducky |
| 2018-07-04 | broken | ducky |
| 2018-07-04 | delete debugging stuff | ducky |
| 2018-07-04 | lol=( | Richard Lin |
| 2018-07-04 | bundle literal mockup, but broken =( | Richard Lin |
| 2018-07-02 | Direct to FIRRTL (#829) | Jack Koenig |
| 2018-06-29 | Catch returns from within when blocks and provide an error message (#842) | Jack Koenig |
| 2018-06-20 | Programmatic Port Creation (#833) | Jack Koenig |
| 2018-06-18 | Fixed UIntToOH(x, 1) invocation with x.width == 0 (#778) | Wesley W. Terpstra |
