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path: root/src/test/scala/chiselTests
AgeCommit message (Expand)Author
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
2019-11-02Tests for anonymous/class-in-module desiredNameSchuyler Eldridge
2019-10-21Add BoringUtils.bore test for internal boringSchuyler Eldridge
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
2019-09-13Fix Queue.apply for size 0 in chisel3._ code (#1177)Jack Koenig
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
2019-08-27Test stack trace trimming for ChiselStageSchuyler Eldridge
2019-08-27Add test that stack trace trimming worksSchuyler Eldridge
2019-08-27Add firrtlTests.Utils methodsSchuyler Eldridge
2019-08-13Add support for asynchronous reset (#1011)Jack Koenig
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
2019-08-08Require target is hardware for Vec.apply(a: UInt)Schuyler Eldridge
2019-07-31Add SInt deprecated compatibility testsSchuyler Eldridge
2019-07-31Add UInt deprecated compatibility testsSchuyler Eldridge
2019-07-31Add Bits deprecated compatibility testsSchuyler Eldridge
2019-07-31Add VecLike deprecated compatibility testsSchuyler Eldridge
2019-07-31Add Wire deprecated compatibility testsSchuyler Eldridge
2019-07-31Add Data deprecated compatibility testsSchuyler Eldridge
2019-07-31Add debug deprecated compatibility testsSchuyler Eldridge
2019-07-31Add Mem/SeqMem deprecated compatibility testsSchuyler Eldridge
2019-07-31Add LFSR16 deprecated compatibility testsSchuyler Eldridge
2019-07-31Add Queue deprecated compatibility testsSchuyler Eldridge
2019-07-31Add Enum deprecated compatibility testsSchuyler Eldridge
2019-07-31Add BitPat deprecated compatibility testsSchuyler Eldridge
2019-07-31Fixup and enable Dummy CompatibilitySpec testSchuyler Eldridge
2019-07-18Support Analog DontCare bulk-connect (#1056)Richard Lin
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
2019-06-24Changed Value macro in ChiselEnum so that it doesn't use deprecated (#1104)Hasan Genc
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
2019-05-22Add stage.phases.AddImplicitOutputAnnotationFileSchuyler Eldridge
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
2019-05-22Add chisel3.stage AnnotationsSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13RawModule with no reset should be able to use withClock method. (#1065)Chick Markley
2019-05-10Augment LFSR16 test to test the enable as wellAndrew Waterman
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
2019-05-09Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)Jack Koenig
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
2019-05-09Add Lfsr testsSchuyler Eldridge
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
2019-05-08Genericize LFSR testing infrastructureSchuyler Eldridge
2019-05-01Make asTypeOf work for bundles with zero-width fields. (#1079)Paul Rigge
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