| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-03-10 | Emit FIRRTL bulkconnects whenever possible (#2381) (#2440) | mergify[bot] |
| 2022-01-10 | Apply scalafmt | Jack Koenig |
| 2020-10-01 | Move Chisel3 to SPDX license conventions (#1604) | Chick Markley |
| 2020-06-22 | Use ChiselStage in Tests | Schuyler Eldridge |
| 2019-05-20 | Repackagecore rebase (#1078) | Jim Lawson |
| 2019-01-25 | WireDefault instead of WireInit, keep WireInit around (#986) | Martin Schoeberl |
| 2018-08-22 | Implement varargs MixedVec API | Edward Wang |
| 2018-08-22 | Make MixedVec wire init consistent with VecInit | Edward Wang |
| 2018-08-22 | Remove dynamic indexing for now | Edward Wang |
| 2018-08-22 | MixedVec: clarify dynamic indexing of heterogeneous elements | Edward Wang |
| 2018-08-22 | MixedVec implementation | Edward Wang |
 |
index : chiselX | |
| Chisel with SFC compatibility |
| summaryrefslogtreecommitdiff |