| Age | Commit message (Collapse) | Author |
|---|
|
* Add HasBlackBoxPath trait
* Use 'setResource' instead of 'addResource'
* Add ScalaDoc
|
|
|
|
* Use test_run_dir for more tests.
* Use official option and DRY.
Make "test_run_dir" the default for ChiselSpec.
Verify output files are created in DriverSpec tests.
|
|
|
|
* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing
* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command
|
