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authorJim Lawson2017-02-28 13:32:38 -0800
committerGitHub2017-02-28 13:32:38 -0800
commit08885d74619328532bc0157ba9cef7f26496b146 (patch)
tree53bd3bd7b4d0b27256700f70b689013a4484674f /src/test/scala/chiselTests/BlackBoxImpl.scala
parentcae110e06d7dfb206e6d50565ee25221b8c6d0a5 (diff)
Use test_run_dir for more tests. (#534)
* Use test_run_dir for more tests. * Use official option and DRY. Make "test_run_dir" the default for ChiselSpec. Verify output files are created in DriverSpec tests.
Diffstat (limited to 'src/test/scala/chiselTests/BlackBoxImpl.scala')
-rw-r--r--src/test/scala/chiselTests/BlackBoxImpl.scala9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
index 9e817486..11d59fe9 100644
--- a/src/test/scala/chiselTests/BlackBoxImpl.scala
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -65,11 +65,12 @@ class UsesBlackBoxMinusViaResource extends Module {
}
class BlackBoxImplSpec extends FreeSpec with Matchers {
+ val targetDir = "test_run_dir"
"BlackBox can have verilator source implementation" - {
"Implementations can be contained in-line" in {
- Driver.execute(Array("-X", "verilog"), () => new UsesBlackBoxAddViaInline) match {
+ Driver.execute(Array("-X", "verilog", "--target-dir", targetDir), () => new UsesBlackBoxAddViaInline) match {
case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
- val verilogOutput = new File("./BlackBoxAdd.v")
+ val verilogOutput = new File(targetDir, "BlackBoxAdd.v")
verilogOutput.exists() should be (true)
verilogOutput.delete()
Succeeded
@@ -78,9 +79,9 @@ class BlackBoxImplSpec extends FreeSpec with Matchers {
}
}
"Implementations can be contained in resource files" in {
- Driver.execute(Array("-X", "low"), () => new UsesBlackBoxMinusViaResource) match {
+ Driver.execute(Array("-X", "low", "--target-dir", targetDir), () => new UsesBlackBoxMinusViaResource) match {
case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
- val verilogOutput = new File("./BlackBoxTest.v")
+ val verilogOutput = new File(targetDir, "BlackBoxTest.v")
verilogOutput.exists() should be (true)
verilogOutput.delete()
Succeeded