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path: root/src/main/scala/chisel3/internal
AgeCommit message (Expand)Author
2016-10-12remove trailing whitespace for annotationsScott Beamer
2016-10-06Fix typo in emitted string.Jim Lawson
2016-10-06Breakup the initial emitted string per @ducky64.Jim Lawson
2016-10-06Remove non-standard sbt-buildinfo settings; write buildinfo to firrtl file.Jim Lawson
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig
2016-08-25fix a bug in setModNameDonggyu Kim
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson