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path: root/src/main/scala/chisel3/internal
AgeCommit message (Expand)Author
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) M...Richard Lin
2018-10-12Strong enums (#892)Hasan Genc
2018-07-02Direct to FIRRTL (#829)Jack Koenig
2017-10-26Invalidateapi (#645)Adam Izraelevitz
2017-08-17Use firrtl elses in elsewhen/otherwise case emission (#510)Albert Magyar
2017-08-11Rename userDir->specifiedDir (#671)Richard Lin
2017-07-28Black box top-level IO fix (#655)Richard Lin
2017-06-26Directions internals mega-refactor (#617)Richard Lin
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-02-08Add Analog typeJack Koenig
2016-11-21Remove deduplication from Chisel (#347)Donggyu
2016-11-18Add support for parameterized BlackBoxesjackkoenig
2016-11-14Add SourceInfo.makeMessage to better use SourceInfo in error messagesJack
2016-10-12remove trailing whitespace for annotationsScott Beamer
2016-10-06Fix typo in emitted string.Jim Lawson
2016-10-06Breakup the initial emitted string per @ducky64.Jim Lawson
2016-10-06Remove non-standard sbt-buildinfo settings; write buildinfo to firrtl file.Jim Lawson
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig
2016-08-25fix a bug in setModNameDonggyu Kim
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
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