chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2016-01-28	Use FIRRTL is invalid construct	Andrew Waterman

2016-01-23	Change implicit clock name to clk to match Chisel2	Andrew Waterman
	This allows us to share Verilog test harnesses between the two.
2016-01-23	Move firrtl subpackage to inside internal subpackage.	jackkoenig

2015-12-11	Add support for printf and asserts, add testbench for asserts and printf	ducky

2015-12-06	Split internal and FIRRTL packages	ducky

2015-11-04	Remove Parameters library and refactor Driver.	Henry Cook
	In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances, this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester. The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed. Further work is needed on individual tests to use assertions instead of .io.error.
2015-10-26	Break Core.scala into bite-sized pieces	ducky