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authorAndrew Waterman2016-01-28 12:05:03 -0800
committerAndrew Waterman2016-01-28 12:05:03 -0800
commit41674d5e130f64d7489fdb8583b8f4ad88b64aeb (patch)
tree9df546ee0291e77aebbae0b752bbde961c752c63 /src/main/scala/Chisel/Module.scala
parentbce4a96934fe8575b71769f2e52a2b75a068d34d (diff)
Use FIRRTL is invalid construct
Diffstat (limited to 'src/main/scala/Chisel/Module.scala')
-rw-r--r--src/main/scala/Chisel/Module.scala8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 2a0f29db..463c2f81 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -20,16 +20,12 @@ object Module {
def apply[T <: Module](bc: => T): T = {
val parent = dynamicContext.currentModule
val m = bc.setRefs()
- // init module outputs
- m._commands prependAll (for (p <- m.io.flatten; if p.dir == OUTPUT)
- yield Connect(p.lref, p.fromInt(0).ref))
+ m._commands.prepend(DefInvalid(m.io.ref)) // init module outputs
dynamicContext.currentModule = parent
val ports = m.computePorts
Builder.components += Component(m, m.name, ports, m._commands)
pushCommand(DefInstance(m, ports))
- // init instance inputs
- for (p <- m.io.flatten; if p.dir == INPUT)
- p := p.fromInt(0)
+ pushCommand(DefInvalid(m.io.ref)) // init instance inputs
m.connectImplicitIOs()
}
}