diff options
| author | Andrew Waterman | 2016-01-23 21:11:09 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-23 21:11:09 -0800 |
| commit | 86a6c6bcdc349f40dcc31bce1931dc7c427da674 (patch) | |
| tree | 37fe805a7eea16e2ae6bdb1d6a516974cfaae89a /src/main/scala/Chisel/Module.scala | |
| parent | b4517e0fb563271464bd40ddf9a46a40fd827da4 (diff) | |
Change implicit clock name to clk to match Chisel2
This allows us to share Verilog test harnesses between the two.
Diffstat (limited to 'src/main/scala/Chisel/Module.scala')
| -rw-r--r-- | src/main/scala/Chisel/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala index 1681f901..2a0f29db 100644 --- a/src/main/scala/Chisel/Module.scala +++ b/src/main/scala/Chisel/Module.scala @@ -60,7 +60,7 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId { private[Chisel] def ref = Builder.globalRefMap(this) private[Chisel] def lref = ref - private def ports = (clock, "clock") :: (reset, "reset") :: (io, "io") :: Nil + private def ports = (clock, "clk") :: (reset, "reset") :: (io, "io") :: Nil private[Chisel] def computePorts = ports map { case (port, name) => val bundleDir = if (port.isFlip) INPUT else OUTPUT |