Change implicit clock name to clk to match Chisel2

This allows us to share Verilog test harnesses between the two.

2 files changed, 5 insertions, 5 deletions

diff --git a/src/main/resources/top.cpp b/src/main/resources/top.cpp
index 075d7085..8bfe2a99 100644
--- a/src/main/resources/top.cpp
+++ b/src/main/resources/top.cpp
@@ -44,10 +44,10 @@ int main(int argc, char** argv) {
       top->reset = 0;   // Deassert reset
     }
     if ((main_time % 10) == 1) {
-      top->clock = 1;       // Toggle clock
+      top->clk = 1;       // Toggle clock
     }
     if ((main_time % 10) == 6) {
-      top->clock = 0;
+      top->clk = 0;
     }
     top->eval();               // Evaluate model
 #if VM_TRACE
@@ -69,10 +69,10 @@ int main(int argc, char** argv) {
   vluint64_t end_time = main_time + 100;
   while (main_time < end_time) {
     if ((main_time % 10) == 1) {
-      top->clock = 1;       // Toggle clock
+      top->clk = 1;       // Toggle clock
     }
     if ((main_time % 10) == 6) {
-      top->clock = 0;
+      top->clk = 0;
     }
     top->eval();               // Evaluate model
 #if VM_TRACE
diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 1681f901..2a0f29db 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -60,7 +60,7 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
   private[Chisel] def ref = Builder.globalRefMap(this)
   private[Chisel] def lref = ref
 
-  private def ports = (clock, "clock") :: (reset, "reset") :: (io, "io") :: Nil
+  private def ports = (clock, "clk") :: (reset, "reset") :: (io, "io") :: Nil
 
   private[Chisel] def computePorts = ports map { case (port, name) =>
     val bundleDir = if (port.isFlip) INPUT else OUTPUT