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authorAndrew Waterman2016-01-23 16:10:22 -0800
committerAndrew Waterman2016-01-23 16:10:22 -0800
commitb4517e0fb563271464bd40ddf9a46a40fd827da4 (patch)
treef8a7c4a9e982590fb140d6945d2e875d0b2e45c1 /src/main
parent780e7c4d2a7e88a3a8ce6f5d7e75e62af6580c6d (diff)
Don't use deprecated constructs
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/Chisel/Aggregate.scala2
-rw-r--r--src/main/scala/Chisel/Bits.scala2
-rw-r--r--src/main/scala/Chisel/util/Arbiter.scala2
-rw-r--r--src/main/scala/Chisel/util/Decoupled.scala2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index 33b71c4e..63df8135 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -156,7 +156,7 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
def write(idx: UInt, data: T): Unit = apply(idx) := data
override def cloneType: this.type =
- Vec(gen, length).asInstanceOf[this.type]
+ Vec(length, gen).asInstanceOf[this.type]
private val t = gen
private[Chisel] def toType: String = s"${t.toType}[$length]"
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index b512bb56..739e6c1b 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -432,7 +432,7 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
def >= (other: SInt): Bool = compop(GreaterEqOp, other)
def != (other: SInt): Bool = compop(NotEqualOp, other)
def === (other: SInt): Bool = compop(EqualOp, other)
- def abs(): UInt = Mux(this < SInt(0), (-this).toUInt, this.toUInt)
+ def abs(): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt)
def << (other: Int): SInt = binop(SInt(this.width + other), ShiftLeftOp, other)
def << (other: BigInt): SInt = this << other.toInt
diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/Chisel/util/Arbiter.scala
index 119b9f5a..2747640f 100644
--- a/src/main/scala/Chisel/util/Arbiter.scala
+++ b/src/main/scala/Chisel/util/Arbiter.scala
@@ -7,7 +7,7 @@ package Chisel
/** An I/O bundle for the Arbiter */
class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
- val in = Vec(Decoupled(gen), n).flip
+ val in = Vec(n, Decoupled(gen)).flip
val out = Decoupled(gen)
val chosen = UInt(OUTPUT, log2Up(n))
}
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala
index b1505887..ca000af9 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/Chisel/util/Decoupled.scala
@@ -82,7 +82,7 @@ class Queue[T <: Data](gen: T, val entries: Int,
{
val io = new QueueIO(gen, entries)
- val ram = Mem(gen, entries)
+ val ram = Mem(entries, gen)
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = Reg(init=Bool(false))