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path: root/core/src/main/scala/chisel3/internal/firrtl
AgeCommit message (Expand)Author
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. (#1944)"...Jack Koenig
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
2021-08-12Add DataView (#1955)Jack Koenig
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-06-28Set refs for ModuleClone and ClonePorts in less hacky wayJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
2021-04-27Introduce VecLiterals (#1834)Chick Markley
2021-04-26Add some error context to Converter .getRefs (#1878)Jack Koenig
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-07-29Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)Adam Izraelevitz
2020-07-22Basic model checking API (#1499)Tom Alcorn
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-03-25Rename subprojects to more canonical namesJack Koenig
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