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* Promote ChiselEnum user APIs from experimental (#2929)
They are commonly used and if we were ever to change them, we will need
to go through a deprecation process anyway.
Note that the EnumAnnotations remain in chisel3.experimental because,
like all Chisel annotation support, they are slated to be deprecated and
removed.
(cherry picked from commit 424e9446f1675fe0168e22bdfbbe85db997376e6)
# Conflicts:
# docs/src/cookbooks/verilog-vs-chisel.md
# docs/src/explanations/chisel-enum.md
* Maintain binary compatbility, use aliases in chisel3 package
* Deprecate the actual classes in chisel3.experimental
* Also fix backport conflicts
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Aditya Naik <aditya.naik@sifive.com>
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(#2690)
* Add a cookbook and publicly visible scaladoc for prefix, noPrefix
(cherry picked from commit ae7dc30b3b99f1fbd91c35f54bc19be7c55f74a3)
Co-authored-by: Megan Wachs <megan@sifive.com>
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Also remove all non-testing uses of chiselName.
(cherry picked from commit 1c5d1b5317a0c9fe7ef9d15138065a817380a1e4)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
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(#2617)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 3ab34cddd8b87c22d5fc31020f10ddb2f1990d51)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
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(backport #2476) (#2479)
* Capture 1:1 mappings of Aggregates inside of views
This is implemented by including any corresponding Aggregates from the
DataView.mapping in the AggregateViewBinding.childMap (which is now of
type Map[Data, Data]).
This enables dynamically indexing Vecs that are themselves elements of
larger Aggregates in views when the corresponding element of the view is
a Vec of the same type. It also increases the number of cases where a
single Target can represent part of a view.
(cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e)
* Add FlatIO API for creating ports from Bundles without a prefix
(cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb)
* [docs] Add FlatIO to the general cookbook
(cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Command:
sbt scalafmtAll
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* DataProducts for Seq and Tuple2-10 in DataProduct companion object
* DataViews for Seq and Tuple 2-10 in DataView companion object
* HWTuple2-10 Bundles in chisel3.experimental
* Implicit conversions from Seq to Vec and Tuple to HWTuple in chisel3.experimental.conversions
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* prototype annotating verif constructs
* switch to final class
* name emissions
* moving BaseSim to experimental
* adding name tests
* fixing quotation escapes
* emitting names, but everything has a default name
* only name things with provided/suggested names
* name every BaseSim node
* removing msg, unused imports
* fixing file exist calls
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package
* Revert reg naming behavior (omit underscore)
* Added documentation and a test
* Addressed reviewer feedback.
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Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above.
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
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