| Age | Commit message (Collapse) | Author |
|---|
|
Co-authored-by: Aditya Naik <aditya.naik@sifive.com>
|
|
#2792) (#2834)
* Fixup and unit tests for D/I of IOs without explicit Input/Output (#2792)
(cherry picked from commit f24a624863f0fc460fd862238688ea8612ffdf5e)
# Conflicts:
# core/src/main/scala/chisel3/Module.scala
* Resolve backport conflicts
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
* Unify Chisel2 and chisel3 directionality (#2634)
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 1aea4ef96466cbe08150d20c85c88b81e4e4f80f)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
# core/src/main/scala/chisel3/Module.scala
# src/test/scala/chiselTests/Direction.scala
* fix up backport
* fix up backport
* clean up diff
* make test order like it was on master
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
|
|
#2829) (#2831)
* Add Aggregate.elementsIterator and micro-optimize
elementsIterator provides a more efficient API for iterating on the
elements of Aggregates. It is especially useful for Records where
getElements returns a Seq and thus eagerly constructs a new
datastructure which may then just be iterated on anyway.
This new elementsIterator API is then used throughout the codebase where
it makes sense.
Also change Vec.getElements to just return the underlying self instead
of constructing a new Seq.
(cherry picked from commit defa440b349031475daeff4024fad04925cccee6)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
# core/src/main/scala/chisel3/Module.scala
# core/src/main/scala/chisel3/experimental/Trace.scala
* Move Aggregate.bind inline into Record.bind
Vec overrides bind and does not call the version in Aggregate so the
version in Aggregate is misleading in that its only ever used by
Records. Now there is no version in Aggregate and the actual
functionality and use is more clear.
(cherry picked from commit b054c30ba47026cb2a9b28c696a0a0a58b1e2ee7)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
* Extract and optimize duplicate checking Record.bind
This replaces an immutable.Map with a single mutable.HashSet and saves
the allocation of # elements Seqs.
(cherry picked from commit 832ea52bc23424bb75b9654422b725a9cafaef40)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
* Add check for Records that define def elements
(cherry picked from commit a4f223415de19e2a732e0b6a8fe681f706a19a56)
* Resolve backport conflicts
* Make elementsIterator final and package private
* Waive false MiMa failure
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
* Define leading '_' as API for creating temporaries
Chisel and FIRRTL have long used signals with names beginning with an
underscore as an API to specify that the name does not really matter.
Tools like Verilator follow a similar convention and exclude signals
with underscore names from waveform dumps by default. With the
introduction of compiler-plugin prefixing in Chisel 3.4, the convention
remained but was hard for users to use unless the unnnamed signal
existed outside of any prefix domain. Notably, unnamed signals are most
useful when creating wires inside of utility methods which almost always
results in the signal ending up with a prefix.
With this commit, Chisel explicitly recognizes signals whos val names
start with an underscore and preserve that underscore regardless of any
prefixing. Chisel will also ignore such underscores when generating
prefixes based on the temporary signal, preventing accidental double
underscores in the names of signals that are prefixed by the temporary.
(cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6)
* Remove unused defaultPrefix argument from _computeName
(cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554)
# Conflicts:
# core/src/main/scala/chisel3/Module.scala
# core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala
* Resolve backport conflicts
* Waive false positive binary compatibility errors
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
option (#2575) (#2579)
* Added ImplicitInvalidate trait with tests
(cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7)
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
|
|
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d)
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
|
|
ExtModule now uses the same namePorts implementation as regular Modules.
Previously, ExtModules only allowed port naming via runtime reflection.
This meant that .suggestName and other naming APIs do not work. It also
breaks FlatIO for ExtModule which is a potential replacement API for
BlackBox's special `val io` handling.
(cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924)
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
Also delete an errant println in InstanceSpec
(cherry picked from commit 3462c54c018a52a377f1c89121b6ed99c5b0ae1d)
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989)
Co-authored-by: Deborah Soung <debs@sifive.com>
|
|
Command:
sbt scalafmtAll
|
|
Exposing more internals of D/I, which are required for supporting D/I with more powerful Chisel libraries:
- Exposing IsClone[_]
- Exposing InstantiableClone[_]
- Gated builders for Instance/Definition
- Unsealing Lookupable, with protected accessors for proto and cloned
|
|
* Add Hierarchy trait
* Add Hierarchy trait
* Add Hierarchy scaladoc
* Add license
* Add isA and tests
* Add back isA
* Add new Select APIs for hierarchy package
* Update scaladoc
* Write outlines for tests
* Add tests and fixes to new Select functions
* Make calculate via lazy val
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Clean up scaladoc
* Add shouldNot compile
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Bugfix all funcs should analyze root too
* Add mdoc, bugfix toDefinition
* Make func private, add scaladoc
* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Made protected vals private
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Address code review comments
* Added additional null check
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
|
|
functions (#2124)
* Migrate nullary funcs to parameterless versions
* Make deprecation message and dummy arguments clear and consistent
Co-authored-by: Megan Wachs <megan@sifive.com>
|
|
Definition/Instance introduced the need for representing the targets of
instances as InstanceTargets. This original implementation changed the
return type of BaseModule.toTarget to express this need. This is a
backwards incompatible change that is actually unnecessary because it is
impossible for users to get references to the internal InstanceClone
objects, instead only accessing such modules via Instance[_] wrappers
and cloned Data. We restored the old API by adding a new internal method
"getTarget" which will give the correct targets for InstanceClones while
maintaining the API of BaseModule.toTarget.
|
|
This introduces a new experimental API for module instantiation that disentagles
elaborating the definition (or implementation) from instantiation of
a given module. This solves Chisel's longstanding reliance on
"Deduplication" for generating Verilog with multiple instances of the
same module.
The new API resides in package chisel3.experimental.hierarchy. Please
see the hierarchy ScalaDoc, documentation, and tests for examples of
use.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
|
|
DataView is a mechanism for "viewing" Scala objects as a subtype of
`Data`. Often, this is useful for viewing one subtype of `Data`, as
another. One can think about a DataView as a cross between a
customizable cast and an untagged union.
A DataView has a Target type `T`, and a View type `V`. DataView requires
that an implementation of `DataProduct` is available for Target types.
DataProduct is a type class that provides a way to iterate on `Data`
children of objects of implementing types.
If a DataView is provided for a type T to a type V, then the function
.viewAs[V] (of type T => V) is available. The object (of type T) returned
by .viewAs is called a "View" and can be used as both an rvalue and an
lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will
connect to the associated field or fields of the underlying Target.
DataView also enables .viewAsSupertype which is available for viewing
Bundles as a parent Bundle type. It is similar to .viewAs but requires
a prototype object of the Target type which will be cloned in order to
create the returned View. .viewAsSupertype maps between the
corresponding fields of the parent and child Bundle types.
|
|
Previously, CloneModuleAsRecord clones would result in the same
BaseModule object coming up multiple times when using APIs like
.instances, .collectDeep, and .getDeep. This was not the intended
behavior and can lead to very subtle bugs.
|
|
|
|
|
|
|
|
|
|
|
|
No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.
* Add MemTypeBinding for port types of Mems
This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.
* Call _onModuleClose on unbound Records
This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
|
|
Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.
Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.
Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
|
|
|
|
|
|
* Bugfix - module name collision for injecting aspect
* Fixed mechanism to avoid module name collisions
* Added comments for reviewer feedback
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
|
|
* Include and check when scoping as part of reg/mem/wire/node bindings
* Allow outdated 'when' behavior of CHIRRTL memory ports with enables
* Extend cross-module / when-visibility checks to all data refs
* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args
* Add basic test cases for cross-module refs / signals escaping when scopes
* Remove illegal cross-module references from existing tests
|
|
Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above.
Co-authored-by: Jack Koenig <koenig@sifive.com>
|
|
|
|
* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
|
